Advance Program of the RISC-V Week
3rd RISC-V Meeting – Keynotes
Seven Chips in Seven Years
The Parallel-Ultra Low Power (PULP) project started in 2013 and from the beginning we wanted to keep its development open source, but we did not know how. In 2015 RISC-V came along with its open ISA and the PULP platform (
pulp-platform.org) emerged from this serendipitous convergence. In this talk, I will look back and, based on seven different SoCs taped out over a seven years period, I will tell the story of how our open source HW approach based on the RISC-V ISA has shaped the way we work and produced exciting results in research and technology transfer. I will then focus on the future challenges and open problems.
Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Università di Bologna. He served as chief architect in STMicroelectronics France. Dr. Benini's research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He has published more than 1000 peer-reviewed papers and five books. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea.
3rd RISC-V Meeting – Presentations
RISC-V and Microkernel-based Operating Systems: Lessons Learned
Before RISC-V, the direct interactions between CPU architects and operating systems architects have been very limited and mostly unidirectional. RISC-V has the ambition to bring these communities much closer to each other.
Besides other goals, some of the main goals of RISC-V are to be open and free (both as in free beer and as in free speech) for designers, users and manufacturers, with strong focus on robustness, safety and security. These goals are shared by the communities around open source microkernel-based operating systems.
This talk summarizes the practical experiences and lessons learned from porting microkernel-basad operating systems such as HelenOS and Genode to RISC-V.
A passionate operating systems developer, enjoying everything from bare metal programming and fixing bugs in the Linux kernel to designing the HelenOS microkernel multiserver operating system and working on its verification of correctness. After spending 10 years in academia as a computer science researcher at Charles University, he switched to a role of principal research engineer at Huawei Technologies. He has been working on HelenOS since 2004.
Preventing timing information leakages from the microarchitecture
Numerous timing side-channels attacks have been proposed in recent years, showing that all shared states inside the CPU microarchitecture are potential threats. Any hardware protection against these threats requires to slightly modify the instruction set architecture (ISA), to communicate the security constraints from the software to the hardware. In this presentation, we will see how the RISC-V ISA can be modified to tackle the problem from first principles, and what the impact is on both hardware and software sides. A new open benchmark measuring timing leakages will also be introduced, making it possible to assess the vulnerability of systems and the effectiveness of implemented mechanisms.
Mathieu Escouteloup is a 3rd year PhD student at Université de Rennes 1 in the CIDRE team at INRIA. He is working on the implementation of secure microarchitectures and on the role of the instruction set architecture to achieve it.
A Compiler Approach to Cyber-Security
By François de Ferrière (STMicroelectronics).
We will present an implementation in the LLVM RISC-V compiler of software countermeasures against single fault or attack at execution time.
Our implementation, named SecSwift, proposes protections at the control-flow, data-flow and memory levels. Code is inserted to verify the correct execution of branch and call instructions, and the content of registers and memory is duplicated for specific resources. Checks are added at some points in the code to verify the correct execution of the program.
The insertion of countermeasures by the compiler compared to hand-written implementations has many advantages, including the activation of full compiler optimizations, a reduced development time and fine tuning of the protection level for performance and code size tradeoffs.
We will present our results on the qualification of these protections on applications, give figures on performance and code size impact, as well as showing annotations reported by the compiler to track protections from source code down to binary code.
These protections are already at production level and will be used in next products developed at STMicroelectronics to replace protections that were previously implemented by hand.
François de Ferrière is a senior compiler developer at STMicrolectronics. François has more than thirty years of experience working on a variety of compilers and on very different aspects including intermediate representations, optimizations and code generation. He has been working with the LVVM compiler for more than five years now on retargeting the LLVM compiler to STMicroelectronics proprietary processors, and since 2017 is focusing on the cyber security domain and started implementing security features in STMicroelectronics compilers.
MaxineVM: Enabling HW/SW Co-design of managed languages on RISC-V
In this talk we will introduce MaxineVM: a metacircular VM for Java applications. MaxineVM is written in Java and enables the easy experimentation and HW/SW codesign with underlying architectures. Recently, RISC-V support has been added to MaxineVM besides the pre-existing compatibility with x86, ARMv7 and AArch64. The creation of a fully open source stack creates new research opportunities for more efficient integration and acceleration of managed languages. To that end, ongoing research of our group which can be extended and evaluated on RISC-V along with some research directions will be discussed
Christos Kotselidis is an Associate Professor at The University of Manchester and a Senior Architect at KTM Innovation. His interests lie in the areas of HW/SW co-design, managed programming languages, heterogeneous hardware acceleration, and embedded systems. He is currently the project lead of TornadoVM and MaxineVM as well as the technical coordinator of the EU H2020 E2Data and ELEGANT projects. In his role at KTM Innovation, he works on the next-generation hardware/software platforms and connected ecosystem of the powered two-wheelers of KTM. Finally, he is a member of the J-Extension Working Group of the RISC-V Foundation.
The RISC-V vector processor in EPI
The European Processor Initiative (EPI) project aims at developing European processor technology for High Performance Computing (HPC) and emerging application areas. Beyond leveraging ARM technology, an important objective of the project is to develop a fully owned implementation of a generic accelerator based on the RISC-V vector extension ISA. The goal of this talk is to describe the fundamental vision behind the design of such accelerator and its architectural features. I will report on the implementation status of the first version of the micro architecture. I will also present the software development vehicle (SDV) frameworks used to steer a holistic co-design approach including operating system and overall system software developments to homogenize the heterogeneous combination of different cores in the overall platform.
Prof. Jesús Labarta received his Ph.D. in Telecommunications Engineering from Universitat Politècnica de Barcelona (UPC) in 1983, where he has been a full professor of Computer Architecture since 1990. He was Director of European Center of Parallelism at Barcelona from 1996 to the creation of BSC in 2005, where he is the Director of the Computer Sciences Dept. His research team has developed performance analysis and prediction tools and pioneering research on how to increase the intelligence embedded in these performance tools. He has also led the development of OmpSs and influenced the task based extension in the OpenMP standard. He has led the BSC cooperation with many IT companies. He is now responsible of the POP center of excellence providing performance assessments to parallel code developers throughout the EU and leads the RISC-V vector accelerator within the EPI project. He has pioneered the use of Artificial Intelligence in performance tools and will promote their use in POP, as well as the AI-centric co-designing of architectures and runtime systems. He was awarded the 2017 Ken Kennedy Award for his seminal contributions to programming models and performance analysis tools for high performance computing, being the First Non US Researcher receiving it.
RISC-V for High Performance General Purpose Cores
In this talk, we will attempt to determine whether high-performance is agnostic of the ISA, or if, on the contrary, the ISA should provide specific facilities if high-performance is to be attained. We will consider several well-known and less well-known techniques that are implemented in modern high-performance x86/ARM cores and attempt to determine if using the RISC-V ISA would facilitate, or, on the contrary, harden, the implementation of such techniques in the context of a flagship general purpose processor core.
Arthur Perais got his PhD from Univ of Rennes 1 in 2015 working on a speculative technique to improve the performance of modern out-of-order processors, value prediction. He then worked on the design of an ARM datacenter chip (Centriq) in Qualcomm Datacenter Technologies (Raleigh, USA) for a year and a half before moving to Microsoft to work on the control plane of a Quantum processor (Raleigh, USA). He then joined CNRS in 2020 and his research interests include high-performance general purpose microarchitecture as well as implications of speculation on security.
Mitigating Spectre Attacks on a RISC-V DBT-Based Processor
Unveiled early 2018, the Spectre vulnerability affects most of the modern high-performance processors. Spectre variants exploit the speculative execution mechanisms and a cache side-channel attack to leak secret data. As of today, the main countermeasures consist of turning off the speculation, which drastically reduces the processor performance. In this work, we focus on a different kind of micro-architecture: the DBT based processors, such as Hybrid-DBT, which is capable of executing RISC-V binaries on a VLIW architecture. Instead of using complex out-of-order (OoO) mechanisms, this core combines a software Dynamic Binary Translation mechanism (DBT) and a parallel in-order architecture. The DBT is in charge of translating and optimizing the binaries before their execution. Studies show that DBT based processors can reach the performance level of OoO cores for regular enough applications. In this paper, we demonstrate that, even if those processors do not use OoO execution, they are still vulnerable to Spectre variants, because of the DBT optimizations. However, we also demonstrate that those systems can easily be patched, as the DBT is done in software and has fine-grained control over the optimization process.
Simon Rokicki has obtained its and PhD degree at Université de Rennes 1 in 2018 and is not working as a research engineer in the CAIRN research group in Rennes. His research interests are Dynamic Binary Translation, Micro-architecture and High-Level Synthesis.
Why programming language research likes new architectures
In this talk we hope to give an overview of some research work and directions from the programming-language community that are relevant to instruction-set design and in general hardware/software interfaces. There is a strong interest in the programming-language community in getting strong, mathematical guarantees about program correctness; we show that is related to questions of secure execution on virtual or not-so-virtual machines, and that it opens the door for fruitful research in lower-level hardware/software systems.
Gabriel Scherer is a permanent researcher at INRIA Saclay, working at the intersection of programming languages and logic. Programming language research studies what can formally be said about programs and programming systems, and how the language in which they are implemented or specified influences these properties. Gabriel has worked in particular on the functional programming language OCaml, with interest in giving strong reasoning tools on programs, in particular to consider proving their correctness.
RISC-V LW-Cryptographic Extension
Security in pervasive connected objects and Internet of Things, is a growing concern. This increasing demand comes with increasing constraints, which led to the development of a new generation of lightweight ciphers algorithms. These algorithms have been developed to allow efficient hardware implementations and their implementation on non specialised microprocessors often lacks efficiency, especially in terms of latency and throughput. This led us to investigate for ways to accelerate the execution of such algorithms on standard processors without implementing full dedicated hardware accelerators. We have chosen to extend the RISC-V ISA by adding a small number of instructions allowing the acceleration of a representative selection of Lightweight Block Ciphers. The majority of these instructions are generic and can be used with a large range of Lightweight Block Ciphers. We present a comparison between a pristine and a modified implementation of a RISC-V core for both area overhead and execution acceleration. For some algorithms, the results show a gain of up to 100x in terms of execution speed. We are currently analysing the security of our extension regarding side channel attacks and working on implementing protection.Etienne Tehrani is a 2nd year PhD student at Telecom-Paris in the LTCI lab working on the implementation and acceleration of Lightweight Block Ciphers.