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Details and proceedings of the 2019 Week are below:

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Tuesday October 1st, First Day of the 2nd RISC-V Meeting

Here is the detailed program. The list of speakers is further down this page.

Location: Espace Van Gogh, 62 quai de la Rapée, Paris.

Time Speaker Title
09h00 Registration
09h45 Christian Fabre & Sébastien Faucou Welcome Opening and Program of the RISC-V Week (slides)
10h00 Tutorials
10h00 Jean-Paul Chaput RISC-V design using Free Open Source Software (slides)
11h00 Break
11h30 Frédéric Pétrot Teaching basic computer architecture, assembly language programming, and operating system design using RISC-V (slides)
12h30 Lunch
13h30 Keynote from the RISC-V Foundation
13h30 Bertrand Tavernier The Momentum and Opportunity of Custom, Open Source Processing
14h15 Break
14h30 Chair: Thierry Collette Session on Open HW Opportunities
14h30 David Bol Ecological transition in ICT: A role for open hardware? (slides)
14h45 Carolynn Bernier A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing (slides)
15h00 Martin Åberg Development of a RV64GC IP core for the GRLIB IP Library (slides)
15h15 All Discussion with David Bol, Carolynn Bernier & Martin Åberg
15h30 Break
15h45 Chair: David Hely Session on Safe and Secure Computing with RISC-V
15h45 Thierry Collette R&D challenges for Safe and Secure RISC-V based computer
16h00 Rafail Psiakis & Baptiste Pecatte RISC-V ISA: Secure-IC's Trojan Horse to Conquer Security
16h15 Fabien Chouteau Alternative languages for safe and secure RISC-V programming (slides)
16h30 All Discussion with Thierry Collette, Rafail Psiakis, Baptiste Pecatte & Fabien Chouteau
16h45 Break
17h00 Chair: Frédéric Pétrot Session on Modeling & Simulation
17h00 Hugues Cassé Verification of SimNML instruction set description using co-simulation (slides)
17h15 Olivier Sentieys Fast and Accurate Vulnerability Analysis of a RISC-V Processor (slides)
17h30 Pierre-Guillaume Le Guay Coarse-grained power modelling and estimation using the Hardware Performance Monitors (HPM) of the RISC-V Rocket core
17h45 All Discussion with Huges Cassé, Olivier Sentieys & Pierre-Guillaume Le Guay
18h00 Closure

Wednesday October 2nd, Second Day of the 2nd RISC-V Meeting

Here is the detailed program. The list of speakers is further down this page.

Location: Espace Van Gogh, 62 quai de la Rapée, Paris.

Time Speaker Title
08h30 Registration
09h00 Keynote on Uniprocessor Performance
09h00 André Seznec It's the Instruction Fetch Front-End, Stupid! (slides)
10h00 Chair: Kevin Martin Session: Towards High Performance
10h00 Matheus Cavalcante Ara: design and implementation of a 1GHz+ 64-bit RISC-V Vector Processor in 22 nm FD-SOI (slides)
10h15 Bernard Goossens An Out-of-Order RISC-V Core Developed with HLS (slides)
10h30 Nima TaheriNejad Open source GPUs: How can RISC-V play a role? (slides)
11h45 All Discussion with Matheus Cavalcante, Bernard Goossens & Nima TaheriNejad
11h00 Break
11h30 Chair: Yves Durand Session: Open Source Cores is an Actual Business
11h30 Ekaterina Berezina Open-source processor IP in the SCRx family of the RISC-V compatible cores by Syntacore (slides)
11h45 Rick O'Connor Open Source Processor IP for High Volume Production SoCs: CORE-V Family of RISC-V cores (slides)
12h00 Yann Loisel Silicon at the speed of software (slides)
12h15 All Discussion with Ekaterina Berezina, Rick O'Connor and Yann Loisel
12h30 Lunch
13h30 Keynote on RISC-V in HPC
13h30 Romain Dolbeau European Processor Initiative: challenges & opportunities for RISC-V accelerators in an HPC platform (slides)
14h30 Chair: Arnaud Tisserand Session on Improving the HW/SW Interface
14h30 Pedro Henrique Penna Nanvix: An Operating System for Lightweight Manycores (slides)
14h45 Yves Durand Enhancing scientific computation using a variable precision FPU with a RISC-V processor (slides)
15h00 Zdeněk Přikryl Enhanced Tools for RISC-V Processor Development and Customization (slides)
15h15 All Discussion with Pedro Henrique Penna, Yves Durand and Zdeněk Přikryl
15h30 Break
16h00 Chair: Olivier Savry Session on Formal Verification
16h00 Sylvain Boulmé Extending the CompCert certified compiler with instruction scheduling and control-flow integrity (slides)
16h15 Sergio Marchese Complete Formal Verification of RISC-V Cores for Trojan-Free Trusted ICs (slides)
16h30 Romain Soulat Formal Proof of RISC-V Cores
16h45 All Discussion with Sylvain Boulmé, Sergio Marchese and Romain Soulat
17h00 Sébastien Faucou Scientific Day: RISC-V for critical embedded systems in Campus de Jussieu on Thursday October 3rd (slides)
17h15 All Wrap Up, Comments & Perspectives
17h30 Closure