RISC-V logo

Registration is now open!



Thursday October 3rd, Scientific Day IRT SE & GDR SOC2: RISC-V for critical embedded systems

Location: Jussieu campus, Paris.

Time Speaker Title
09h00 Registration & Welcome
09h30 Sébastien Pillement (GDR SOC2) Presentation of GDR SOC2
09h40 Marie-Hélène Deredempt (IRT Saint-Exupéry) Presentation of IRT Saint-Exupéry
9h50 Michael Chapman (Cortus) RISC-V in embedded applications
10h45 Antoine Certain (Airbus Defence and Space) What does the space industry expect from RISC-V?
11h15 Jan Andersson (Cobham Gaisler) Development of a RV64GC IP core for the GRLIB IP Library
12h00 Lunch
14h00 Denis Dutoit (CEA LETI) European Processor Initiative: First steps towards a made-in-Europe high-performance microprocessor
14h45 Eric Jenn (IRT Saint-Exupéry) Achieving determinism and performance on the RISC-V FlexPRET Processor
15h30 Break
15h45 Daniel Große (University of Bremen & DFKI GmbH) RISC-V based Virtual Prototype: An Open Source Platform for Modeling and Verification
16h30 Romain Soulat (Thales Research & Technology) Formal Verification of RISC-V Implementation Designs
17h15 Closure