The Program of the Scientific Day: RISC-V for critical embedded systems
- Thursday October 3rd, from 9:00 to 17:15.
Thursday October 3rd, Scientific Day IRT SE & GDR SOC2: RISC-V for critical embedded systems
Location: Jussieu campus, Paris.
|09h30||Sébastien Pillement||Presentation of GDR SOC2|
|09h40||Marie-Hélène Deredempt||Presentation of IRT Saint-Exupéry|
|09h50||Michael Chapman||RISC-V in embedded applications|
|10h50||Antoine Certain||What does the space industry expect from RISC-V?|
|11h20||Johan Klockars||Development of a RV64GC IP core for the GRLIB IP Library|
|14h00||Denis Dutoit||European Processor Initiative: First steps towards a made-in-Europe high-performance microprocessor|
|14h45||Eric Jenn||Achieving determinism and performance on the RISC-V FlexPRET Processor|
|15h45||Daniel Große||RISC-V based Virtual Prototype: An Open Source Platform for Modeling and Verification|
|16h30||Romain Soulat||Formal Verification of RISC-V Implementation Designs|
Speakers of the Scientifc Day on RISC-V for critical embedded systems
RISC-V in embedded applications
Cortus is a French ASIC design company with a very large selection of IPs available including processors (Cortus proprietary ISA, RISC-V ISA), and many other Digital, Analog/RF and Security (HW & SW) which together with its ASIC Design expertise enables it to architect, design and implement innovative chips for its clients.
Cortus provides a comprehensive and complete toolchain package such as debugger, compiler, IDE, etc, for all the chips it develops.
To facilitate the work of software developers, Cortus can also provide FPGA prototypes.
Cortus has designed and is designing chips and modules for customers incorporating RISC-V processors in the following application fields: Satellite, Avionics, Automotive, IoT, Hardware Security Module, HPC (outside Europe)
Michael Chapman is the creator of microprocessors, micro-controllers, CAN (Controller Area Network) and System C.
He has worked on a Silicon on Saphire radiation hard microprocessor chip set for Marconi Space and Defence, a pure asynchronous chip for Acorn computers, and developed all the initial CAN implementations including the Intel 82526 and those for Bosch internal implementations, Philips, Motorola, National, NEC, Siemens as well as the Intel 82527 and those on Intel MCUs. He also developed MCUs for engine management and ABS.
He designed a new generation 16 bit micro-controller for Siemens and modeled that controller in 'C'. The simulation environment he created escaped from Siemens and became the foundation of System C.
In 2003, he created the first Cortus processor which is at the heart of security solutions used in bank cards, SIM cards, e-passport and is the root of trust in many devices including Blackberry, Intel, Fujitsu, etc.
What does the space industry expect from RISC-V?
By Antoine Certain, Airbus Defence & Space
The space industry has some particularities which makes the usage of COTS components quite difficult. But, with the emergence of new space designs based on COTS, the space industry open its doors to a bigger ecosystem. And the RISC V ecosystem could answer to the major requirements of spacecraft design. This presentation will present the main requirements such industry expect from a core IP.
Antoine CERTAIN is an experienced hardware and software architect on embedded data-handling applications on spacecraft. He has gained large scale of space knowledge thanks to several projects for ESA, CNES and internally to Airbus Defence and Space. He is now team leader of the R&D On board data processing team of Airbus Defence and Space in Toulouse, FR.
Development of a RV64GC IP core for the GRLIB IP Library
By Johan Klockars, Cobham Gaisler
Cobham Gaisler is a world leader for space computing solutions where the company provides radiation tolerant system-on-chip devices based around the LEON processors. The building blocks for these devices are also available as IP cores from the company in an IP library named GRLIB. Cobham Gaisler is currently developing a RV64GC core that will be provided as part of GRLIB. The presentation will cover features of the IP core and how it fits with existing peripherals, with technical items we see missing in the specification.
Johan Klockars has a MSc in Computer Science & Engineering and is a Hardware Engineer at Cobham Gaisler, working on their new RISC-V CPU core. He has been doing embedded systems development for 20 years: image processing and communications protocols in FPGAs, real-time systems, WiFi networking, device drivers, etc.
European Processor Initiative: First step towards a made-in-Europe high-performance microprocessor
By Denis Dutoit, CEA LETI
The European Processor Initiative (EPI) is a project funded by the European Commission, whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications. The project started in December 2018 and aims to deliver a high-performance, low-power processor, implementing ARM based general purpose processors and RISC-V based specific accelerators. The EPI processor will also meet high security and safety requirements. This will be achieved through intensive use of simulation, development of a complete software stack and tape-out in the most advanced semiconductor process node.
After an introduction on High Performance Computing new challenges and associated technology/architecture evolution, the presentation will highlight the EPI position statement on generic computing, accelerator with RISC-V and design methodology. The presentation will end with EPI’s roadmap towards a wide range of applications from Exascale computing to embedded HPC.
Denis Dutoit, EPI global architecture leader, Architecture, IC Design and Embedded Software Division, Leti
Denis Dutoit joined CEA-Leti in 2009, after working for STMicroelectronics and STEricsson. In CEA-Leti, he has been involved in System-on-a-Chip architecture for computing and 3D Integrated Circuit projects. After defining the Leti’s roadmap of technologies and solutions for advanced computing, Denis Dutoit is now involved in European Projects in High Performance Computing as coordinator, project leader and SoC architect.
Achieving determinism and performance on the RISC-V FlexPRET Processor
By Eric Jenn, IRT Saint-Exupéry
Performance improvement usually comes at the cost of temporal determinism. Trading better average performance for a loss of predictability is sometimes acceptable, but it is not for safety-critical applications where the time at which a value is produced is often as important as the value itself. In this talk, we address the question of temporal determinism, which is a prerequisite to dependability. We show how we combine a deterministic programming model with a deterministic hardware architecture and an “holistic” optimization process to achieve both performance and dependability. This work is applied on the MultiPRET processor, a "multicore" declination of the RISC-V FlexPRET PREcision Timed Architecture (PRET) proposed by the University of California at Berkeley.
Dr Eric Jenn is a research engineer at Thales AVS. He is currently managing the Critical Applications on Predictable High-Performance Computing Architectures (CAPHCA) collaborative research project at IRT Saint-Exupéry in Toulouse. Dr Jenn has been working in the area of safety critical systems for around 30 years, both on the analysis and development of nuclear and avionics systems. His interests cover all aspects of the development of dependable real-time systems, including certification, system modeling and design, real-time software development, formal verification, and microarchitecture design. He has participated in many collaborative research projects involving academic and industrial partners, including GUARDS, Diana, SPICES, ESPASS, etc.
RISC-V based Virtual Prototype: An Open Source Platform for Modeling and Verification
We propose an open source RISC-V based Virtual Prototype (VP) under MIT license, available at
http://www.systemc-verification.org/riscv-vp. Our VP is implemented in standard compliant SystemC using a generic bus system with TLM 2.0 communication. Our VP provides a 32 and 64 bit RISC-V core with different privilege levels, the RISC-V CLINT and PLIC interrupt controllers and an essential set of peripherals. It supports simulation of (mixed 32 and 64 bit) multi-core platforms and provides SW debug and coverage measurement capabilities. We support FreeRTOS, Zephyr and Linux operating systems. Our VP allows a significantly faster simulation compared to RTL, while being more accurate than existing ISSs. The VP has been designed as configurable and extensible platform. For example we provide the configuration for the RISC-V HiFive1 board from SiFive.
Daniel Große is a Senior Researcher at the University of Bremen and the German Research Center for Artificial Intelligence (DFKI) Bremen, Germany. His research interests include verification, virtual prototyping, debugging and synthesis. He has published more than 120 papers in peer-reviewed journals and conferences and served in program committees of numerous conferences, such as DAC, ICCAD, DATE and CODES+ISSS. He received best paper awards at FDL 2007, DVCon Europe 2018, and ICCAD 2018.
Formal Verification of RISC-V Implementation Designs
By Romain Soulat, Thales Research & Technology
Formal verification of hardware designs is a classical application of model checking in industry. RISC-V cores can be formally verified for functional correctness and framework already exist to automatically perform that kind of verification. When designs includes safety or security mechanisms, special additional verification requirements can be added to formally verify that those mechanisms performs correctly against threats or feared events.Romain Soulat is working at Thales Research and Technology (TRT) on the application of formal methods. He obtained his PhD. from Ecole Normale Supérieure Paris-Saclay in 2014 on the subject of formal verification of timed automata and controllers. In 2014, he joined the Critical Embedded Systems Laboratory at TRT to work on the topic of formal verification. His current research focus on model checking at system or implementation levels, numerical accuracy analysis and formal verification of AI-based systems.
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