RISC-V logo

The event is now over… See you next year!



Time Speaker Title
09h00 Registration
09h45 Christian Fabre & Sébastien Faucou Welcome Opening and Program of the RISC-V Week (slides)
10h00 Tutorials
10h00 Jean-Paul Chaput RISC-V design using Free Open Source Software
11h00 Break
11h30 Frédéric Pétrot Teaching basic computer architecture, assembly language programming, and operating system design using RISC-V (slides)
12h30 Lunch
13h30 Keynote from the RISC-V Foundation
13h30 Bertrand Tavernier The Momentum and Opportunity of Custom, Open Source Processing
14h15 Break
14h30 Chair: Thierry Collette Session on Open HW Opportunities
14h30 David Bol Ecological transition in ICT: A role for open hardware?
14h45 Carolynn Bernier A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing (slides)
15h00 Martin Åberg Development of a RV64GC IP core for the GRLIB IP Library
15h15 All Discussion with David Bol, Carolynn Bernier & Jan Andersson
15h30 Break
15h45 Chair: David Hely Session on Safe and Secure Computing with RISC-V
15h45 Thierry Collette R&D challenges for Safe and Secure RISC-V based computer
16h00 Rafail Psiakis & Baptiste Pecatte RISC-V ISA: Secure-IC's Trojan Horse to Conquer Security
16h15 Fabien Chouteau Alternative languages for safe and secure RISC-V programming
16h30 All Discussion with Thierry Collette, Rafail Psiakis, Baptiste Pecatte & Fabien Chouteau
16h45 Break
17h00 Chair: Frédéric Pétrot Session on Modeling & Simulation
17h00 Hugues Cassé Verification of SimNML instruction set description using co-simulation
17h15 Olivier Sentieys Fast and Accurate Vulnerability Analysis of a RISC-V Processor (slides)
17h30 Pierre-Guillaume Le Guay Coarse-grained power modelling and estimation using the Hardware Performance Monitors (HPM) of the RISC-V Rocket core
17h45 All Discussion with Huges Cassé, Olivier Sentieys & Pierre-Guillaume Le Guay
18h00 Closure