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Details and proceedings of the 2019 Week are below:

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Time Speaker Title
08h30 Registration
09h00 Keynote on Uniprocessor Performance
09h00 André Seznec It's the Instruction Fetch Front-End, Stupid! (slides)
10h00 Chair: Kevin Martin Session: Towards High Performance
10h00 Matheus Cavalcante Ara: design and implementation of a 1GHz+ 64-bit RISC-V Vector Processor in 22 nm FD-SOI (slides)
10h15 Bernard Goossens An Out-of-Order RISC-V Core Developed with HLS (slides)
10h30 Nima TaheriNejad Open source GPUs: How can RISC-V play a role? (slides)
11h45 All Discussion with Matheus Cavalcante, Bernard Goossens & Nima TaheriNejad
11h00 Break
11h30 Chair: Yves Durand Session: Open Source Cores is an Actual Business
11h30 Ekaterina Berezina Open-source processor IP in the SCRx family of the RISC-V compatible cores by Syntacore (slides)
11h45 Rick O'Connor Open Source Processor IP for High Volume Production SoCs: CORE-V Family of RISC-V cores (slides)
12h00 Yann Loisel Silicon at the speed of software (slides)
12h15 All Discussion with Ekaterina Berezina, Rick O'Connor and Yann Loisel
12h30 Lunch
13h30 Keynote on RISC-V in HPC
13h30 Romain Dolbeau European Processor Initiative: challenges & opportunities for RISC-V accelerators in an HPC platform (slides)
14h30 Chair: Arnaud Tisserand Session on Improving the HW/SW Interface
14h30 Pedro Henrique Penna Nanvix: An Operating System for Lightweight Manycores (slides)
14h45 Yves Durand Enhancing scientific computation using a variable precision FPU with a RISC-V processor (slides)
15h00 Zdeněk Přikryl Enhanced Tools for RISC-V Processor Development and Customization (slides)
15h15 All Discussion with Pedro Henrique Penna, Yves Durand and Zdeněk Přikryl
15h30 Break
16h00 Chair: Olivier Savry Session on Formal Verification
16h00 Sylvain Boulmé Extending the CompCert certified compiler with instruction scheduling and control-flow integrity (slides)
16h15 Sergio Marchese Complete Formal Verification of RISC-V Cores for Trojan-Free Trusted ICs (slides)
16h30 Romain Soulat Formal Proof of RISC-V Cores
16h45 All Discussion with Sylvain Boulmé, Sergio Marchese and Romain Soulat
17h00 Sébastien Faucou Scientific Day: RISC-V for critical embedded systems in Campus de Jussieu on Thursday October 3rd (slides)
17h15 All Wrap Up, Comments & Perspectives
17h30 Closure