Your RISC-V Week

The RISC-V Week merges two events, from October 1st to 3rd 2019 in Paris:

• The 2nd RISC-V Meeting, organised by IRT Nanoelec and the CEA, will take place at Espace Van Gogh, 62 quai de la Rapée:
  • Tuesday October 1st, from 09:45 to 18:00 – registration from 9:00.
  • Wednesday October 2nd, from 9:00 to 17:30 – registration from 8:30.
  This event is sponsored by:

       

• The Scientific Day of IRT SE & GDR SOC2: RISC-V for critical embedded systems organised by IRT St-Exupéry and GDR SOC2, will take place on the Jussieu campus:
  • Thursday October 3rd, from 9:00 to 17:15.

2nd RISC-V Meeting

The RISC-V architecture, which comes from academia, is challenging several communities.

• It opens the architecture and hardware design communities to the dynamics of open source;
• Language, compilation, operating system, security or safety communities can now influence the definition of hardware architectures;
• More generally, it allows hardware, software and system communities to experiment together.

After the first 1st RISC-V Meeting on academic opportunities held in Grenoble in October 2018, the second edition will take place in Paris on October 1st and 2nd 2019. They are open to the academic and industrial worlds and they will address several important topics:

1. The impact of the arrival of open-source on the design of systems on a chip (SoC), embedded systems or cyber-physics (CPS).
2. Legal and strategic intellectual property (IP) issues, ranging from public management of hardware open source code, to sovereignty issues.
3. Identifying collaboration points between the hardware, software, and systems communities.
4. Facilitating collaboration between academic research and industry.

To allow as much time as possible for exchanges the core of the program is made up of multiple sessions, with a small number of short contributions followed by a time for group discussion. The program also includes a number of tutorials on key RISC-V issues and solutions, and high-level keynotes.

Program Committee

The Program Committee comprises:

• Thierry Collette, Thales R&T
• Christian Fabre, CEA, chair
• Eric Flamand, GreenWaves Technologies
• Pierre Gobin, STMicroelectronics
• Nicolas Hili, IRT Saint-Exupéry
• David Hély, INPG/LCIS
• Mathieu Jan, CEA
• Kevin Martin, UBS/Lab-STICC
• Ivan Miró-Panadès, CEA
• Ahmed Ould El Hacen, Wisekey
• Thomas Peyret, CEA
• Frédéric Pétrot, INPG/TIMA
• Olivier Savry, CEA, co-chair
• Olivier Sentieys, INRIA

Organisation Committee

The Organisation Committee comprises:

• Jean-Philippe Blanc, IRT Nanoelec
• Damien Couroussé, CEA
• Laurent-Frédéric Ducreux, IRT Nanoelec, co-chair
• Christian Fabre, CEA, chair
• Mathieu Jan, CEA
• Didier Louis, CEA
• Thomas Peyret, CEA
• Olivier Savry, CEA, co-chair

Contact

The Organising Committee can be reached at: organisation@open-src-soc.org.

Scientific Day IRT St-Exupéry & GDR SOC2: RISC-V for critical embedded systems

IRT Saint-Exupéry & GDR SOC2 continue their cooperation with the organisation of their 3rd scientific day gathering industry and academia on critical embedded systems.

This year, the scientific day will be held in Paris, in partnership with the 2nd RISC-V Meeting and as part of the RISC-V Week. It will focus on the opportunities offered by RISC-V and open hardware solutions for critical embedded systems.

The day will include extensive presentations by guest speakers from academia and industry on the following topics:

• Industrial needs and requirements
• Hardware design
• Design tools for critical systems

Organisation Commitee

The Organisation Committee comprises: Philippe Cuenot (IRT St-Exupéry, Continental), Sébastien Faucou (LS2N, Université de Nantes), Maxime Pelcat (IETR, INSA de Rennes).

Contact

The Organisation Committee from the Scientific Day of IRT Saint-Exupéry & GDR SOC2 can be reached at contact-3oct@open-src-soc.org.