The 2nd RISC-V Week will gather two events over three days:
|Tuesday 30th March||3rd RISC-V Meeting (1st Day)|
|Wednesday 31st March||3rd RISC-V Meeting (2nd Day)|
|Thursday 1st April||OpenHW Day|
“3rd RISC-V Meeting” on March 30-31
The RISC-V architecture, which comes from academia, is challenging several communities.
- It opens the architecture and hardware design communities to the dynamics of open source;
- It eases the introduction of new technologies in the verification tool flow of IPs;
- Language, compilation, operating system, security or safety communities can now influence the definition of hardware architectures;
- More generally, it allows hardware, software and system communities to experiment together.
After the first 1st RISC-V Meeting in Grenoble in October 2018, and the 2nd RISC-V Meeting in Paris in October 2019, this 3rd RISC-V Meeting was originally scheduled to happen in real life in Rennes in November 2020. Due to the current pandemic it has been postponed and will finally take place on line and, if conditions allow, partly in real life with local sites in Rennes, Palaiseau (SW of Paris), and Grenoble. It will last two days: Tuesday March 30th and Wednesday March 31st, 2021.
This 3rd iteration will be open to students, academics and industrials.
The program will be made of multiple sessions, with a small number of short contributions followed by a time for group discussion. The program will also include a number of tutorials on key RISC-V issues and solutions, and high-level keynotes.
The Organisation Committee comprises:
- Marion Andrillat, CEA
- Édith Blin, INRIA
- Thierry Collette, Thales
- Damien Couroussé, CEA
- Romain Dolbeau, SiPearl
- Denis Dutoit, CEA
- Christian Fabre, CEA, chair
- Sébastien Faucou, Univ. de Nantes
- Pierre Gobin, STMicroelectronics
- Magaly Gouttebroze, CEA
- David Hély, Grenoble INP & LCIS
- Mathieu Jan, CEA
- Kevin Martin, UBS & Lab-STICC
- Christophe Monat, STMicroelectronics
- David Monniaux, VERIMAG
- Maxime Pelcat, INSA Rennes & IETR
- Frédéric Pétrot, Grenoble INP & TIMA
- Jean-Luc Poupat, Airbus
- Olivier Savry, CEA
- Olivier Sentieys, INRIA, co-chair
- Assia Tria, CEA
The organizers of the “3rd RISC-V Meeting” are:
The Organising Committee can be reached at:
“OpenHW Day” on April 1st
OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.
The “OpenHW Day” will present an interactive update on the CORE-V IP Cores, running projects and supporting infrastructure.
A detailed agenda to follow shortly.