This is the program for the two days “3rd RISC-V Meeting”:
This great program was possible thanks to our organisers and sponsors.
Tuesday, March 30
Wednesday, March 31
Speakers of Tuesday March 30
Welcome Address from the IRT Nanoelec
Keynote – seL4 and RISC-V: Taking security to the next level
Security of computer systems is a persistent problem, with mainstream operating systems having thousands of hidden vulnerabilities resulting from implementation bugs, and new attacks discovered all the time. Recent attacks, such as Spectre, show that the problem is even worse than classic software bugs, demonstrating that information leakage through timing channels is a mainstream threat. The seL4 microkernel was the first operating system kernel with a formal, machine-checked proof of functional correctness of the implementation, demonstrating that bug-free software is possible. Follow-up research has extended this to proofs of security enforcement down to the binary, and demonstrations that seL4 can protect real-world systems from attacks. I will explain seL4 and its verification story, which was recently extended to the RISC-V architecture. I will then cover our current research on time protection, the principled prevention of timing channels. I show how all Intel and ARM processors we examined exhibit timing channels that are impossible to close, calling for improved hardware support. We have subsequently shown that an exisiting open-source RISC-V core can be easily extended to provide such support at low cost, making that core the first processor on which the OS can prevent timing channels. We are working with the RISC-V community on getting the required mechanism standardised, while concurrently working on formally verifying our prevention mechanisms. At least one company is in the process of producing chips that support our mechanisms, a great demonstration of the power of an open architecture with open-source implementations.
Gernot Heiser is Scientia (distinguished) Professor and John Lions Chair of Operating Systems at UNSW Sydney and Chief Research Scientist at CSIRO’s Data61. His research interest are in operating systems, real-time systems, security and safety. He is the founder and past leader of Data61’s Trustworthy Systems group, which pioneered large-scale formal verification of systems code, specifically the design, implementation and formal verification of the seL4 microkernel; seL4 is now being designed into real-world security- and safety-critical systems. Heiser's former company Open Kernel Labs, acquired by General Dynamics in 2012, marketed the OKL4 microkernel, which shipped on billions of mobile wireless chips and more recently ships on the secure enclave of all iOS devices. He presently serves as Chief Scientist, Software, of HENSOLDT Cyber, a Munich-based company providing a secure hardware-software stack for embedded and cyber-physical systems. Gernot is a Fellow of the ACM, the IEEE and the Australian Academy of Technology and Engineering (ATSE) and an ACM Distinguished Lecturer
Preventing timing information leakages from the microarchitecture
Numerous timing side-channels attacks have been proposed in recent years, showing that all shared states inside the CPU microarchitecture are potential threats. Any hardware protection against these threats requires to slightly modify the instruction set architecture (ISA), to communicate the security constraints from the software to the hardware. In this presentation, we will see how the RISC-V ISA can be modified to tackle the problem from first principles, and what the impact is on both hardware and software sides. A new open benchmark measuring timing leakages will also be introduced, making it possible to assess the vulnerability of systems and the effectiveness of implemented mechanisms.
Mathieu Escouteloup is a 3rd year PhD student at Université de Rennes 1 in the CIDRE team at INRIA. He is working on the implementation of secure microarchitectures and on the role of the instruction set architecture to achieve it.
Leveraging the LLVM framework and memory encryption to provide low overhead runtime pointer integrity checking
Memory safety problems (buffer overflows, use-after-free) are the root cause of most security issues in today’s programs. Most of these programs are written in unsafe languages (C, C++), which allow raw pointers manipulation. Fortunately, safe languages (Rust, Ada) are getting more and more adoption in the industry, which definitely reduces the number of vulnerabilities. However, these languages would usually only provide guarantees at compile-time, under a perfect execution model. What would happen if a clock glitch is injected on the circuit and a stack variable copy instruction is skipped? It could definitely lead to a buffer overflow. In this talk, we will present a countermeasure that provides run-time pointer integrity verification. It builds on top of a memory encryption and integrity scheme and some code instrumentation that we implemented in the LLVM compiler. Aside from the countermeasure, we will present our validation framework and some performance results.
Thomas Hiscock is a researcher at the hardware security laboratory of CEA Grenoble (CEA LETI/DSYS/LSOSP). He is the lead maintainer of the laboratory infrastructure for side-channel analysis and fault-injection. He contributes to security testing (on the hardware side) of pre-production devices of CEA industrial partners. Currently, his research topics include the design of secure processors (against hardware attacks) through the Nanotrust (IRT-PULSE) project, side-channel analysis, fault-injection as well as micro-architectural attacks (mainly cache timing attacks).
Mitigating Spectre Attacks on a RISC-V DBT-Based Processor
Unveiled early 2018, the Spectre vulnerability affects most of the modern high-performance processors. Spectre variants exploit the speculative execution mechanisms and a cache side-channel attack to leak secret data. As of today, the main countermeasures consist of turning off the speculation, which drastically reduces the processor performance. In this work, we focus on a different kind of micro-architecture: the DBT based processors, such as Hybrid-DBT, which is capable of executing RISC-V binaries on a VLIW architecture. Instead of using complex out-of-order (OoO) mechanisms, this core combines a software Dynamic Binary Translation mechanism (DBT) and a parallel in-order architecture. The DBT is in charge of translating and optimizing the binaries before their execution. Studies show that DBT based processors can reach the performance level of OoO cores for regular enough applications. In this paper, we demonstrate that, even if those processors do not use OoO execution, they are still vulnerable to Spectre variants, because of the DBT optimizations. However, we also demonstrate that those systems can easily be patched, as the DBT is done in software and has fine-grained control over the optimization process.
Simon Rokicki has obtained its and PhD degree at Université de Rennes 1 in 2018 and is not working as a research engineer in the CAIRN research group in Rennes. His research interests are Dynamic Binary Translation, Micro-architecture and High-Level Synthesis.
RISC-V in China
Mainland China has become the main market for semiconductors, attracting companies, talents and IP to the country. With the so-called “War on Huawei”, the Chinese government doubled down on independent innovation and mastery of the key technologies. In particular, it is crucial for China to emancipate themselves from the ARM/x86 duopoly and gain autonomy in designing processors and cores. In that respect, RISC-V represent a unique opportunity for Chinese companies to develop their own cores and IP, and reshuffle the cards in the market. We wrote on extensive study of Chinese RISC-V ecosystem, from associations, universities, research centers as well as companies, in order to better understand who are the players of that ecosystem.
Pierre Sel is a deputy representative of CEA in China, focusing on digital technologies. Relying on his background in Chinese studies as well as researcher, he joined CEA’s team in Beijing to conduct field work and in depth monitoring of the Chinese semiconductor industry and innovation landscape, in close coordination with the embassy other’s services.
Didier Guy is an international expert in technological innovation, with a strong focus on Information and Communications Technology. Relying on his experiences in several countries – including China – with Orange, a major telecommunications operator, with roles including R&D scientist and team leader in the field of distributed computing, innovation projects director and marketing director, he joined Expertise France in 2018 to handle technological innovation questions with the "High Education, Research and Innovation" section of the Embassy of France in China.
CMP Services for ASIC Prototyping, An Overview
CMP is a service organization enabling prototype and low volume production fabrications on industrial process lines. Services are provided at very attractive costs thanks to MPW runs (Multi-Project Wafer) using cost sharing for masks and wafer fabrications. CMP is pioneering such service offer since 1981. Technology processes offered include CMOS, SiGe/BiCMOS, High-Voltage CMOS, BCD, SOI, MEMS, Si-Photonics, NVM, etc. CMP distributes free of charge and under NDA the design-kit and design-rules manual for each process technology. Design-kits contain the PDK, and comprehensive set of standard-cells libraries and I/O libraries. Prototype fabrication is provided with a delivery of typically 40 samples, either as bare dies or packaged
CMP can handle, in cooperation with the semiconductor foundries, low volume productions i.e. from some hundreds to thousands parts, delivered on dedicated wafers, or as bare dies, or packaged.
CMP service is available to Universities, Research Labs, and Industrial companies.
660 customers from 71 countries have been served, more than 8480 projects have been prototyped through 1180 MPW runs and 74 different technologies have been interfaced.
Dr. Kholdoun TORKI received his Ph.D. degree in Microelectronics in 1990 from the INPG Grenoble, France. He is currently Director of CMP, since 2020. His research interest includes CAD tools design-flows and methodologies, 2.5/3D-IC System Integration. He is currently involved in Europractice European project, where CMP is partner and service center. He authored and co-authored more than 120 scientific papers, designed more than 30 ASIC circuits, and since 1986 has participated and/or coordinated 15 European and National projects. He is co-founder and member of the board of directors of iRoC Technologies.
Tutorial – An Introduction to the Official Formal Specification of the RISC-V ISA
By Rishiyur S. Nikhil (Bluespec, Inc.).
We present an overview of the official formal specification of the RISC-V ISA. RISC-V International has committed that this will be the official, definitive ISA spec, unlike previous ISAs where specs were text documents. It will be the standard for measuring functional correctness of all RISC-V implementations (including hardware cores, software simulators and emulators). The spec is ready for the base RV32 and RV64 ISAs, extensions M, A, F, D and C, and the privileged spec (User/ Supervisor/ Machine modes, and virtual memory). It will evolve to keep track of new extensions. It is written in Sail, an open-source domain specific language for ISA specs. Sail is engineered to be accessible to anyone familiar with text-style ISA specs. The spec is executable, by running it through the Sail compiler (written in OCaml), and is fast enough to boot Linux in minutes. The formal spec also opens up research into formally verified hardware implementations, compilers and simulators, and extensions for security and accelerators.
Rishiyur Nikhil chaired the technical group in the RISC-V Foundation that developed the RISC-V ISA formal spec. He is CTO and co-founder of Bluespec, Inc., which provides RISC-V cores and RISC-V system verification and development tools. Bluespec also developed the open-source BSV and BH High-Level Hardware Design Languages (HLHDLs), using ideas from Haskell and atomic transactions.
His degrees are from U. Pennsylvania (CS PhD) and IIT Kanpur (EE BTech). His interests and R&D career (at MIT, Digital Equipment Corp. and some startups) span full systems, from formal methods and high-level programming languages to CPUs and system micro-architectures.
A Compiler Approach to Cyber-Security
By François de Ferrière (STMicroelectronics).
We will present an implementation in the LLVM RISC-V compiler of software countermeasures against single fault or attack at execution time.
Our implementation, named SecSwift, proposes protections at the control-flow, data-flow and memory levels. Code is inserted to verify the correct execution of branch and call instructions, and the content of registers and memory is duplicated for specific resources. Checks are added at some points in the code to verify the correct execution of the program.
The insertion of countermeasures by the compiler compared to hand-written implementations has many advantages, including the activation of full compiler optimizations, a reduced development time and fine tuning of the protection level for performance and code size tradeoffs.
We will present our results on the qualification of these protections on applications, give figures on performance and code size impact, as well as showing annotations reported by the compiler to track protections from source code down to binary code.
These protections are already at production level and will be used in next products developed at STMicroelectronics to replace protections that were previously implemented by hand.
François de Ferrière is a senior compiler developer at STMicrolectronics. François has more than thirty years of experience working on a variety of compilers and on very different aspects including intermediate representations, optimizations and code generation. He has been working with the LVVM compiler for more than five years now on retargeting the LLVM compiler to STMicroelectronics proprietary processors, and since 2017 is focusing on the cyber security domain and started implementing security features in STMicroelectronics compilers.
Scheduling for the CompCert verified compiler
CompCert is a C compiler with a mathematical, machine-checked proof that the semantics of the assembly code produced matches that of the source code. It therefore avoids all middle-end bugs that occasionally crop up in the optimization phases of traditional compilers such as gcc. The mainline version of CompCert targets x86, x86-64, PPC32, PPC64, ARM, AArch64, RiscV-32 and RiscV-64.
The mainline version of CompCert does not schedule instruction according to processor pipeline constraints, which is very important for performance on in-order processors.
We have extended CompCert with a backend for the Kalray KVX VLIW processor, various optimizations (e.g. loop-invariant code motion), pre-pass scheduling for KVX, various Risc-V and AArch64 cores, and peephole optimizations plus post-pass scheduling for KVX and some AArch64 cores, with notable performance boost compared to mainline CompCert.
In this talk, I will introduce the general framework of formal proof of CompCert, pre-pass and post-pass scheduling, and what kind of help we could get from core developers to improve performance.
David Monniaux is senior researcher at CNRS and director of the VERIMAG laboratory, jointly operated by CNRS, Université Grenoble Alpes and Grenoble-INP. He has worked on various aspects of static analysis, abstract interpretation and decision procedures, and is one of the co-authors of the Astrée static analyzer, with users in avionics, automotive and other industries. He has lately engaged in the development of optimizations and extensions of the CompCert formally verified compiler.
Why programming language research likes new architectures
In this talk we hope to give an overview of some research work and directions from the programming-language community that are relevant to instruction-set design and in general hardware/software interfaces. There is a strong interest in the programming-language community in getting strong, mathematical guarantees about program correctness; we show that is related to questions of secure execution on virtual or not-so-virtual machines, and that it opens the door for fruitful research in lower-level hardware/software systems.
Gabriel Scherer is a permanent researcher at INRIA Saclay, working at the intersection of programming languages and logic. Programming language research studies what can formally be said about programs and programming systems, and how the language in which they are implemented or specified influences these properties. Gabriel has worked in particular on the functional programming language OCaml, with interest in giving strong reasoning tools on programs, in particular to consider proving their correctness.
NOEL-V RISC-V Processor latest development roadmap and applications
By Nils-Johan Wessman (Cobham Gaisler AB).
The NOEL-V is a RV32 and RV64 processor model with a configurable set of extensions. NOEL-V is available as part of the GRLIB IP library, which is available in a free open-source version and under a traditional commercial license. The talk will provide an update on the NOEL-V development roadmap and specifically report on the work being done on implementation of the H extension. NOEL-V is currently being used within the De-RISC and SELENE H2020 projects and the presentation will report on the current architectures developed within these projects.
Mr Nils-Johan Wessman is a Sr. Digital Design Engineer at Cobham Gaisler in Sweden. He has an M.Sc. in Electrical Engineering and is the lead engineer for the NOEL-V processor model development. Nils-Johan has a long experience in digital IP core development and SoC design and has several implementations that are used within spacecraft avionics.
RISC-V and Microkernel-based Operating Systems: Lessons Learned
Before RISC-V, the direct interactions between CPU architects and operating systems architects have been very limited and mostly unidirectional. RISC-V has the ambition to bring these communities much closer to each other.
Besides other goals, some of the main goals of RISC-V are to be open and free (both as in free beer and as in free speech) for designers, users and manufacturers, with strong focus on robustness, safety and security. These goals are shared by the communities around open source microkernel-based operating systems.
This talk summarizes the practical experiences and lessons learned from porting microkernel-basad operating systems such as HelenOS and Genode to RISC-V.
A passionate operating systems developer, enjoying everything from bare metal programming and fixing bugs in the Linux kernel to designing the HelenOS microkernel multiserver operating system and working on its verification of correctness. After spending 10 years in academia as a computer science researcher at Charles University, he switched to a role of principal research engineer at Huawei Technologies. He has been working on HelenOS since 2004.
MaxineVM: Enabling HW/SW Co-design of managed languages on RISC-V
In this talk we will introduce MaxineVM: a metacircular VM for Java applications. MaxineVM is written in Java and enables the easy experimentation and HW/SW codesign with underlying architectures. Recently, RISC-V support has been added to MaxineVM besides the pre-existing compatibility with x86, ARMv7 and AArch64. The creation of a fully open source stack creates new research opportunities for more efficient integration and acceleration of managed languages. To that end, ongoing research of our group which can be extended and evaluated on RISC-V along with some research directions will be discussed
Christos Kotselidis is an Associate Professor at The University of Manchester and a Senior Architect at KTM Innovation. His interests lie in the areas of HW/SW co-design, managed programming languages, heterogeneous hardware acceleration, and embedded systems. He is currently the project lead of TornadoVM and MaxineVM as well as the technical coordinator of the EU H2020 E2Data and ELEGANT projects. In his role at KTM Innovation, he works on the next-generation hardware/software platforms and connected ecosystem of the powered two-wheelers of KTM. Finally, he is a member of the J-Extension Working Group of the RISC-V Foundation.
Speakers of Wednesday March 31
Keynote – Seven Chips in Seven Years
The Parallel-Ultra Low Power (PULP) project started in 2013 and from the beginning we wanted to keep its development open source, but we did not know how. In 2015 RISC-V came along with its open ISA and the PULP platform (
pulp-platform.org) emerged from this serendipitous convergence. In this talk, I will look back and, based on seven different SoCs taped out over a seven years period, I will tell the story of how our open source HW approach based on the RISC-V ISA has shaped the way we work and produced exciting results in research and technology transfer. I will then focus on the future challenges and open problems.
Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Università di Bologna. He served as chief architect in STMicroelectronics France. Dr. Benini's research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He has published more than 1000 peer-reviewed papers and five books. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea.
Syntacore open source & commercial RISC-V IP solutions
By Alexander Redkin (Syntacore).
We describe family of the state-of-the-art RISC-V compatible microprocessor core IP developed by Syntacore with specific focus on our 64 bit product line and roadmap. Overall, SCRx family now includes eight industry-grade cores with comprehensive features, targeted at different applications: from compact SCR1 MCU core, which is one of the first fully open industry-grade RISC-V compatible cores to the high-performance 64 bit Linux-capable SCR7 core with SMP and coherency support. SCRx cores support instantiation in heterogeneous multicore clusters with atomics and memory coherency. In the session, we further detail cores features, benchmarks and collateral availability.
Alexander Redkin is Executive Director and co-founder at Syntacore. Prior to establishing Syntacore in 2015, Alexander had more than 15 years of experience in semiconductor industry in senior engineering and management roles, including more than 12 years at Intel R&D, where he contributed both to the number of research projects and volume semiconductor products development. Alexander’s research interests are future SoC architectures and heterogeneous platforms with specific focus on emerging workloads analysis and acceleration.
SemiDynamics' High Bandwidth RISC-V Cores
In this talk, SemiDynamics will discuss its family of high-bandwidth RISC-V application cores, targeted at application domains such as Machine Learning, Recommendation Systems, Sparse Computation, HPC and Key-Value Store. We will cover the “gazzillion misses” technology capable of sustaining a high request rate to memory and describe the in-order core (Avispado) and the out-of-order core (Atrevido). We will also describe the open vector interface that allows connecting a RISC-V vector unit to SemiDynamics cores.
Roger Espasa got his Phd in Computer Science from Universitat Politècnica de Barcelona (UPC) in 1997. Between 1999 and 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture (see the Tarantula paper). In 2002, the Alpha team was acquired by Intel. Between 2002 and 2014 Roger worked at Intel developing a vector extension for the x86 ISA which was initially deployed in the Larrabee and Knight's Corner product and then became the AVX-512 extension. Roger also led the team implementing the texture sampling unit for the original Larrabee chip. Roger also worked on the core for the Knight's Landing product (14nm) and led the core for the follow-on Knights Hill 10nm product. In 2014, Roger joined Broadcom where he worked on a from-scratch ARMv8 wide out-of-order core supporting both A64 and A32. In 2016 Roger founded SemiDynamics Technology Services where he is working on RISC-V cores. Among other things, SemiDynamics architected and designed the 1024+ core machine learning 7nm SoC for Esperanto Technologies. Roger has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions. Roger holds 9 patents with 41 international filings.
Neox, RISC-V based GPU Processor
By Iakovos Stamoulis (Think Silicon, an Applied Materials Company).
The NEOX AI IP Series presents a flexible and scalable solution that enables the rapid deployment of AI, machine learning, and GPGPU applications on resource-constrained devices while significantly improving battery life. This design leverages the modularity and openness of the RISC-V ecosystem to provide a rich set of support tools that accelerate application-specific solutions.
Iakovos has over 20 years of experience in the Computer Graphics and Semiconductor industry. He has a strong technology track record in bringing new technologies from concept to implementation and subsequently to commercial products. He has worked for Advanced Rendering Technology in the UK and USA, where he co-engineered the first Ray Tracing Graphics Engine chip and in Greece where he successfully led teams of engineers in Atmel's Multimedia and Communication Business Unit to the tapeout of numerous devices that reached mass production in the multimedia and wireless markets. He has a D.Phil from the Centre for VLSI and Computer Graphics of the University of Sussex, UK.
Codasip - Solving your on-chip processing challenges
Codasip is based in the heart of Europe with several active R&D centres. It offers a continuously growing offering of RISC-V intellectual property (IP) cores and processor design tools to address your computing challenges on SoCs as well as making sure you will keep the recipes of your differentiators secret. Based on patented university work, Codasip Studio combined with the commercial processor soft IPs, can significantly improve your time to market and make the best usage of the hardware you will tape out. Our vision is to provide a codesign experience enabling the freedom to unleash your differentiators whilst fighting against the ecosystem fragmentation so that RISC-V continues to expand quickly and sustainably. Beyond the description of the offering, the speaker will bring to the attention of the audience the challenges of the expected and necessarily growing complexity in the RISC-V ecosystem.
Codasip is expanding and Mélaine Facon is the Director of the Design Centre of Codasip which is up and running since mid 2020 in Sophia Antipolis. He has over 18 years of experience in numerous segments of the semiconductor IP industry including more than 11 years at Arm. He has a VLSI engineering degree and worked in many positions such as HDL designer, project and program manager of complex IP development and productisation.
The RISC-V vector processor in EPI
The European Processor Initiative (EPI) project aims at developing European processor technology for High Performance Computing (HPC) and emerging application areas. Beyond leveraging ARM technology, an important objective of the project is to develop a fully owned implementation of a generic accelerator based on the RISC-V vector extension ISA. The goal of this talk is to describe the fundamental vision behind the design of such accelerator and its architectural features. I will report on the implementation status of the first version of the micro architecture. I will also present the software development vehicle (SDV) frameworks used to steer a holistic co-design approach including operating system and overall system software developments to homogenize the heterogeneous combination of different cores in the overall platform.
Prof. Jesús Labarta received his Ph.D. in Telecommunications Engineering from Universitat Politècnica de Barcelona (UPC) in 1983, where he has been a full professor of Computer Architecture since 1990. He was Director of European Center of Parallelism at Barcelona from 1996 to the creation of BSC in 2005, where he is the Director of the Computer Sciences Dept. His research team has developed performance analysis and prediction tools and pioneering research on how to increase the intelligence embedded in these performance tools. He has also led the development of OmpSs and influenced the task based extension in the OpenMP standard. He has led the BSC cooperation with many IT companies. He is now responsible of the POP center of excellence providing performance assessments to parallel code developers throughout the EU and leads the RISC-V vector accelerator within the EPI project. He has pioneered the use of Artificial Intelligence in performance tools and will promote their use in POP, as well as the AI-centric co-designing of architectures and runtime systems. He was awarded the 2017 Ken Kennedy Award for his seminal contributions to programming models and performance analysis tools for high performance computing, being the First Non US Researcher receiving it.
RISC-V for High Performance General Purpose Cores
In this talk, we will attempt to determine whether high-performance is agnostic of the ISA, or if, on the contrary, the ISA should provide specific facilities if high-performance is to be attained. We will consider several well-known and less well-known techniques that are implemented in modern high-performance x86/ARM cores and attempt to determine if using the RISC-V ISA would facilitate, or, on the contrary, harden, the implementation of such techniques in the context of a flagship general purpose processor core.
Arthur Perais got his PhD from Univ of Rennes 1 in 2015 working on a speculative technique to improve the performance of modern out-of-order processors, value prediction. He then worked on the design of an ARM datacenter chip (Centriq) in Qualcomm Datacenter Technologies (Raleigh, USA) for a year and a half before moving to Microsoft to work on the control plane of a Quantum processor (Raleigh, USA). He then joined CNRS in 2020 and his research interests include high-performance general purpose microarchitecture as well as implications of speculation on security.
RV64X, An Open Source RISC-V GPU ISA Extension
RV64X is designed to be an open-source ISA extension to the RISC-V Vector architecture. It will be structured as a layered set of extensions on top of RISC-V Vector in the spirit of RISC-V, including 2D raster, 2D vector, 3D graphics and Ray Tracing.
A group of enthusiasts with leading expertise in hardware and firmware design are spearheading the effort. Some key elements of the design will be a fused CPU-GPU ISA, unified memory architecture, user-configurable register files, scalability, conformance to industry standards such as OpenGL ES and Vulkan’s SPIR-V and an open-source driver.
This will enable fabrication of low-cost devices that service the gamut from IoT and edge applications to mobile and desktop systems to cloud based servers.
Atif Zafar, MD has had a passion for computer graphics for over 30 years. A practicing medical doctor, he started working with Silicon Graphics and SUN workstations in the 1990s and moving on to PC based fixed-function graphics accelerators and later GPUs in the 2000s. He is an entrepreneur with 9 startups in diverse fields including high-performance mobile supercomputing, custom ASIC IP, educational, maker and retro-gaming hardware, medical devices, energy systems and consumer privacy.
Tutorial – Toward a Libre Self-Hosting RISC-V Computer
Together, we will explore the construction of a Free/Libre computer system from the ground up, so that we may completely trust that the entirety of its hardware and software behavior is fully attributable to freely available HDL (Hardware Description Language) and software sources. More importantly, all compilers and associated toolchains involved in the system's construction must also be Free and Libre software, and be themselves buildable and runnable on the target system, resulting in no external (non-free) dependencies, a.k.a. a self-hosting software+hardware ecosystem. This tutorial will show how such a computer can be built based on the LiteX SoC, and a RocketChip (RISC-V) CPU, on top of Lattice ECP5 FPGAs programmable using a Free/Libre toolchain (Yosys/Trellis/Nextpnr).
For those willing to follow the tutorial hands on on their own system, the recommanded set-up is this: (1) Machine: a Fedora 32 – real or virtual; (2) How-to-build: steps outlined at
https://github.com/litex-hub/linux-on-litex-rocket; (3) For the FPGA board (optional), two options: (3.a) Free all the way down either the
LambdaConcept ecpix5 (85k version) available here, or the
Trellisboard (not available for purchase, AFAIK); (3.b) Xilinx based-boards, such as
genesys2 with Vivado already installed.
Gabriel Somlo is a Cybersecurity Researcher at the CERT Division of Carnegie Mellon's SEI. In his several past lives, he was a UNIX admin, acquired a Ph.D. in Computer Science, became a network architect, and later an IT director. Throughout his career, he has maintained a passion for decentralized computing systems that place control and responsibility in the hands of end users. In his spare time, Gabriel enjoys contributing to free/open-source software and hardware projects.
A dynamic, authenticated secure debug scheme on RISC-V cores
By Frank Lhermet, Yann Loisel (SiFive).
Security and testability to the platform are usually antinomic. Users and customers usually shall either choose for debug features or for security but both available look like impossible. Debug mechanisms shall not become attack paths.
The objective of the presented scheme is to be flexible and adapted to different use cases. Therefore, the main objective for this scheme is to authenticate the operator. For that reason, the use of cryptography is critical as cryptographic primitives enable various services. Furthermore, it paves the way to formally proving the security strength of the proposal. In order to ease this flexibility requirement, the solution is a mix of hardware and software mechanisms, where the software makes the various use cases possible without the need to modify the hardware. Finally, compliance with the RISC-V debug specifications is a key feature.
After receiving his degree in Cryptography, Yann started work at the French DoD, finally reaching the position of Cryptanalysis Team Manager. He then successively joined SCM Microsystems GmbH, managing the security of smart card readers and DVB payTV decoders, then Innova Card,a fabless company designing secure microcontrollers, acting as Chief Security Officer and joined Maxim Integrated as Security Architect, managing all security-related topics including physical protection, cryptography, applications security, and certifications. He’s now Principal Security Architect at SiFive, in charge of defining the platforms security architecture for SiFive RISC-V chips.
Accelerating Data Processing with RISC-V P, V and Custom Extensions
By Charlie Su (Andes Technology Corporation).
With its open, modular and extensible ISA, RISC-V architecture is leading the innovations for all computing devices, in particular for the emerging applications of 5G, AIoT, Automotive, Networking and Storage. In this talk, we will look into RISC-V architecture support to accelerate data processing for applications ranging from audio, voice, image, to video, vision, communication and AI. The RISC-V P extension or packed SIMD/DSP targets for fixed-point computations for audio, voice, image and slow video while the RISC-V V or Vector extension aims for higher data-rate applications with both fixed-point and floating-point instructions. For those interested in pursuing the ultimate performance efficient for domain-specific architecture, RISC-V’s custom extensibility creates a whole new opportunity for innovations. We will also examine how to unlock such potential.
Dr Charlie Su is the cofounder, CTO and EVP of Andes. He led Andes to develop processor IP solutions with its own ISA before adopting RISC-V 4 years ago. The annual volume of Andes-Embedded SoC has now surpassed 2 billion in 2020. Charlie spent over 12 years in the Silicon Valley at Sun, C-Cube, SGI/MIPS, and Intergraph. He made key contributions to successful processors such as the Sun multi-core multi-threading Ultrasparc processors, the C-Cube MPEG codec processors, the MIPS out-of-order R10K families, and the Intergraph Clipper VLIW processor. Before starting Andes in 2005, he led the processor IP development in Faraday Technology for 2 years.
RISC-V LW-Cryptographic Extension
Security in pervasive connected objects and Internet of Things, is a growing concern. This increasing demand comes with increasing constraints, which led to the development of a new generation of lightweight ciphers algorithms. These algorithms have been developed to allow efficient hardware implementations and their implementation on non specialised microprocessors often lacks efficiency, especially in terms of latency and throughput. This led us to investigate for ways to accelerate the execution of such algorithms on standard processors without implementing full dedicated hardware accelerators. We have chosen to extend the RISC-V ISA by adding a small number of instructions allowing the acceleration of a representative selection of Lightweight Block Ciphers. The majority of these instructions are generic and can be used with a large range of Lightweight Block Ciphers. We present a comparison between a pristine and a modified implementation of a RISC-V core for both area overhead and execution acceleration. For some algorithms, the results show a gain of up to 100x in terms of execution speed. We are currently analysing the security of our extension regarding side channel attacks and working on implementing protection.
Etienne Tehrani is a 2nd year PhD student at Telecom-Paris in the LTCI lab working on the implementation and acceleration of Lightweight Block Ciphers.
Tutorial – OpenTitan, the Technology and the Community
OpenTitan is a first-of-its-kind technical project, an open source silicon root of trust, made possible by our emphasis on partnerships and in developing a collaborative engineering methodology that works for silicon. Since publicly launching over one year ago, we have more than doubled most meaningful project metrics, including the size of both implementation and documentation content, along with the number of unique contributors. I will review the OpenTitan root of trust in this talk, as well as our approach to creating silicon products based on the open source project. I will discuss our organizational structure and some specific examples of how our approach has proven successful in an open silicon context.
Dominic Rizzo founded and leads the OpenTitan effort at Google, the world’s first open source silicon root of trust. He is also responsible for Google’s Enterprise Security Key, the industry’s first FIPS-certified U2F security key. He is a member of the Board of Directors for the UK-based lowRISC CIC.
Dominic holds a B.S. in Aerospace Engineering from the Massachusetts Institute of Technology and an M.S. in Computer Science from the California Institute of Technology. He maintains active collaborations with researchers at MIT, Stanford, the University of Cambridge and other institutions focused on secure silicon, authentication, and formal methods for security.
Overview of the OpenHW Group and the “OpenHW Day”
By Rick O'Connor (The OpenHW Group).
In this presentation I will provide an introduction to the OpenHW Group, a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software.
I will also present the program of the second event of the “2nd RISC-V Week” that is the “OpenHW Day” scheduled the day after, i.e. on April 1st.Rick O'Connor is Founder and serves as President & CEO of the OpenHW Group. Previously Rick was Executive Director of the RISC-V Foundation. Founded by Rick in 2015 with the support of over 40 Founding Members, the RISC-V Foundation currently comprises more than 400 members building an open, collaborative community of software and hardware innovators powering processor innovation. With many years of Executive level management experience in semiconductor and systems companies, Rick possesses a unique combination of business and technical skills and was responsible for the development of dozens of products accounting for over $750 million in revenue. Rick holds an Executive MBA degree from the University of Ottawa, Canada and is an honors graduate of the faculty of Electronics Engineering Technology at Algonquin College, Canada.
Organizers and Sponsors
Organizers of the “2nd RISC-V Week”
The organizers of the “3rd RISC-V Meeting” are:
Sponsors of the “3rd RISC-V Meeting”
The Gold sponsors of the “3rd RISC-V Meeting” are: