2nd RISC-V Week Banner

Two RISC-V events over 3 days!

The program is online and registration is open!

Online + Rennes, Paris (Palaiseau) & Grenoble

The OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

The “OpenHW Day” presents an interactive update on the CORE-V IP Cores, running projects and supporting infrastructure.

Thursday, April 1st

Time Speaker, Chair Title
08h30 Rick O'Connor Keynote – Open Source History, Trends & Adoption
09h30 Davide Schiavone, Jérôme Quévremont CORE-V Cores Roadmap
10h30 Robert Balas, Jeremy Bennett, Simon Davidmann, Alexander Fedorov, Alfredo Herrera, Ivan Kravets, Philipp Krones, Jessica Mills, Shteryana Shopova OpenHW SW Task Group Projects
12h00 Lunch
12h30 Rick O'Connor. Luca Benini, Fabien Clermidy, Simon Davidmann, John D. Davis, Mike Milinkovich, Matthias Völker, Tim Whitfield. Panel – OpenHW Europe
13h30 Florian Zaruba CORE-V MCU & APU
14h30 Break
14h45 Aimee Sutton, Lee Moore, Mike Thompson, Steve Richmond, Greg Tumbush CORE-V Verif: Hands On
16h15 Rick O'Connor. Sebastian Ahmed, John Martin, Robert Oshana, Tim Saxe, Bertrand Tavernier Panel – OpenHW IP Adopters
17h15 Duncan Bees OpenHW Project Execution
17h45 Rick O'Connor OpenHW Day Wrap Up
18h00 End of OpenHW Day

Speakers of Thursday April 1st

Keynote – Keynote: Open Source History, Trends & Adoption

By Rick O'Connor (OpenHW Group).

This talk will provide a brief History of Open Source SW (OSS), an introduction to RISC-V, the free & open Instruction Set Architecture. Challenges with SoC design and Open Source IP will also be covered as will OpenHW Group Governance and adoption of CORE-V Family of open source RISC-V cores.

Rick O'Connor is Founder and serves as President & CEO of the OpenHW Group. Previously Rick was Executive Director of the RISC-V Foundation. Founded by Rick in 2015 with the support of over 40 Founding Members, the RISC-V Foundation currently comprises more than 400 members building an open, collaborative community of software and hardware innovators powering processor innovation. With many years of Executive level management experience in semiconductor and systems companies, Rick possesses a unique combination of business and technical skills and was responsible for the development of dozens of products accounting for over $750 million in revenue. Rick holds an Executive MBA degree from the University of Ottawa, Canada and is an honors graduate of the faculty of Electronics Engineering Technology at Algonquin College, Canada.

CORE-V Cores Roadmap

By Davide Schiavone (OpenHW Group) and Jérôme Quévremont (Thales Research & Technology).

This session will present the roadmap for the CORE-V Family of open-source RISC-V cores as maintained by the OpenHW Cores Task Group. Originally developed by the PULP Platform team at ETH Zurich under the names “RI5CY” and “Ariane”, the CORE-V Family consists of a range of embedded and application class open-source RISC-V cores for use in high-volume production SoCs.

Pasquale Davide Schiavone is the Director of Eng. of Core Task Group (design team) of the OpenHW Group. He obtained the PhD title at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group in 2020, and the BSc. and MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016, respectively. His main activities are the RISC-V CPU design and low-power energy-efficient computer architectures for smart systems and human-machine interfaces. He visited the Centre of Bio-Inspired Technology at Imperial College London in the Next Generation Neural Interfaces group from January to June 2018. Since the PhD, he delivers training workshops to companies and universities.

Jérôme Quévremont is RISC-V and open hardware project leader at Thales Research and Technology (TRT), Palaiseau, France. He serves as the OpenHW Group Cores TG vice-chair and the technical leader of the CVA6 application core project. He is also the chairman of the Functional Safety special interest group at RISC-V International. His past experience includes the development of telecom and security integrated circuits at Texas Instruments and Thales Communications then the management of a development lab specialized in secure- and crypto-chips, mostly in ASIC technologies. He joined TRT in 2020.

OpenHW SW Task Group Projects

GCC and LLVM by: Jessica Mills (Embecosm), Philipp Krones (Embecosm).

FreeRTOS by: Robert Balas (ETH Zurich), Shteryana Shopova (Embecosm).

Eclipse CDT and PlatformIO by: Alexander Fedorov (ArSysOp), Ivan Kravets (PlatformIO Labs).

OVPSim and Verilator Modeling by: Simon Davidmann (Imperas Software Ltd), Alfredo Herrera (aLean-Tec).

Future software projects by: Jeremy Bennett (Embecosm).

Questions & answers by all speakers.

Any silicon chip is only as good as the software ecosystem which accompanies it. The software Task Group's mission is to drive the creation of this ecosystem for OpenHW Group processors. Not just developing key software elements needed, but also encouraging the growth of a thriving commercial community which can develop and maintain this software for the long term. In this session we'll hear about the four main pillars of our work: compilers, operating systems, IDEs and modeling. The presenters are the engineering leads for their projects. They will focus on the technology they are developing, and demonstrate the software in operation. We hope that having listened to these talks you will be inspired, not just to use the tools, but to join the collaborative teams from around the world who are developing them.

Jeremy Bennett chairs the OpenHW Group Software Task Group. He is Chief Executive of Embecosm, a consultancy developing open source compilers, operating systems, silicon chip models and AI/ML solutions based in the UK and Germany. A former academic, Dr. Bennett is author of the standard textbook “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003). He also serves as Chair of the British Computer Society Open Source Specialist Group.

Simon Davidmann is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org). Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Automation, Simon was an executive or European GM with 5 US-based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.

Alexander Fedorov is ArSysOp Founder and CEO, active Open Source contributor and conference speaker. After 20 years of working in the area of IDE and tools with TogetherSoft, Borland, Micro Focus, Embarcadero, NXP and others, he switched to consulting on architecture and development for Eclipse-based solutions.

Alfredo Herrera is an electrical engineer with over 20 years of experience in digital design and verification of Integrated Circuits, validation of 3G/4G mobile communication base stations, technical project management and optical networking communications. Alfredo completed a Master degree in Systems Science on Open Source Hardware for sustainable development at the university of Ottawa. He served in the IEEE SA Open Source Committee and is currently a member of the IEEE SA North America Advisor Committee. Alfredo was part of the initial verification team for OpenHW group RV32E40P and is currently the technical lead for the modeling of the OpenHW group MCU for the Verilator free and open source CAD tool. Alfredo is the father of three daughters and he lives in Ottawa with his wife Marieke.

Ivan Kravets is founder and CEO of PlatformIO Labs (https://piolabs.org). He founded PlatformIO in 2014 to solve the problem of multi-platform development in the embedded systems industry. Their unique philosophy gives embedded developers true freedom – to personally decide which operating system, integrated development environment, and hardware to use. At PlatformIO Labs, they believe the embedded systems industry desperately needs reinvention. Not only are the IDEs and tools built with technology from the 1990s, but the complex requirements for embedded engineers.

Philipp Krones is a Software Tool Chain and AI Engineer at Embecosm. He is the team lead of the official linter of the Rust programming language. In the Open HW Group he works on the Clang/LLVM compiler support for the CV32E40P core.

Jessica Mills is a Software Tool Chain Engineer at Embecosm, developers of open source compilers, operating systems, silicon chip models and AI/ML solutions. She graduated from the University of Leeds with a masters degree in Electronics and Computer Engineering. Jessica leads the CORE-V GNU Tools Project.

Shteryana Shopova received her Bachelor's degree in Computer Science at the university of Sofia, Bulgaria. She has been working as a software engineer for more than fifteen years now, specializing in embedded and networking applications. She joined the FreeBSD development team in 2006, and has been since promoting FreeBSD and open source software in various ways, including mentoring a couple of Google Summer of Code projects and co-organizing a local conference dedicated to open source software & hardware in her home city, Sofia. Keen about open source technologies, she developed a special interest in RISC-V over the last couple of years.

Other bio TBA.

Panel – OpenHW Europe

Moderated by Rick O'Connor (OpenHW Group).

Panelists: Luca Benini (ETH Zürich, Univ. Bologna), Fabien Clermidy (CEA), Simon Davidmann (Imperas Software Ltd), John D. Davis (BSC), Mike Milinkovich (Eclipse Foundation), Norbert Schuhmann (Fraunhofer IIS), Tim Whitfield (Imagination Technologies Ltd).

This panel will explore the role open-source ecosystems can play in support of national technological sovereignty goals. The new Horizon Europe program will have an increasing emphasis on Open Hardware and RISC-V across all computing domains from high performance to low-power, from supercomputers to the microcontrollers for the IoT. Also, with the objective of the European Processor Initiative (EPI) being the development of European know-how on the design and construction of processors for high-performance computing and thus allowing Europe technological sovereignty, what role can or should the OpenHW Group play? What are key considerations as OpenHW Europe is created to help address these objectives?

Luca Benini holds the chair of Digital Circuits and Systems at ETHZ and is Full Professor at the Universita di Bologna. He served as chief architect at STMicroelectronics, France. Dr. Benini's research interests are in energy-efficient parallel computing systems, smart sensing micro-systems, and machine learning hardware. He is the founder and leader of the Open PULP platform. He is a Fellow of the IEEE and of the ACM, and a member of Academia Europaea.

Fabien Clermidy is currently heading the digital architecture and IC design department in the research technology division of CEA. In this position, he develops the hardware and software computing strategy for High-Performance Computing, Artificial Intelligence, Cybersecurity and Cyber-Physical-Systems in relation with system developments in automotive, factory of future, avionics or defense and new nanotechnologies such as 3D chip-stacking, embedded Non-Volatile-Memories, photonic and quantum computing. Fabien has been working in CEA since 2000, holding different positions as project leader and manager of different teams. He is also a senior expert with a PhD supervisor degree and has published more than 80 papers at major conferences such as ISSCC and DAC.

Simon Davidmann is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org). Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Automation, Simon was an executive or European GM with 5 US-based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.

John D. Davis is the director of LOCA, the Laboratory for Open Computer Architecture, and the lead PI for MEEP and eProcessor projects at the BSC. He is also a member of the board of directors for the OpenHW Group. He has published over 30-refereed conference and journal papers in Computer Architecture (ASIC and FPGA-based domain-specific accelerators, non-volatile memories and processor design), Distributed Systems, and Bioinformatics. He holds over 35 issued or pending patents in the USA and multiple international filings. He has designed and built distributed storage systems in research and as products. John has led the entire product strategy, roadmap, and execution for a big data and analytics company. He has worked in research at Microsoft Research, where he also co-advised 4 PhDs, as well as at large and small companies like Sun Microsystems, Pure Storage, and Bigstream. John holds a B.S. in Computer Science and Engineering (University of Washington) and an M.S. and Ph.D. in Electrical Engineering (Stanford University).

Mike Milinkovich has been involved in the software industry for over thirty years, doing everything from software engineering, to product management, to IP licensing. He has been the Executive Director of the Eclipse Foundation since 2004. In that role he is responsible for supporting both the Eclipse open-source community and its commercial ecosystem.

Norbert Schuhmann studied electrical engineering and computer science at the University of Erlangen-Nürnberg. From 1988 to 1995 he worked as a senior digital design engineer and system architect at Fraunhofer IIS. From 1995 to 1999 he was self-employed as a consultant for ASIC and SoC development. In 1999 he returned to Fraunhofer IIS and has been running the digital integrated systems group since then. His key interests are high speed data processing architectures and complex low power system on chip developments in latest silicon technologies.

Tim Whitfield is responsible for all aspects of engineering at Imagination Technologies, from concept to delivery of innovative hardware and software products. He has had an active interest in open source hardware for many years, especially how it disrupts the industry and models for commercial adoption. After spending his early career at GEC and Fujitsu, Tim spent nearly 20 years at Arm, initially working in engineering before holding a number of senior leadership roles encompassing business strategy and engineering as well as five years living and working in Taiwan. With over 25 years of experience in the industry Tim has strong background in hardware system design and design methodology as well as the semiconductor business and ecosystem.

Others bios TBA


By Florian Zaruba (OpenHW Group).

In this talk, we will give an overview of the OpenHW CORE-V open-source embedded MCU and application class APU platforms. The CORE-V MCU is built around the CORE-V CV32E40P, a four-stage, in-order, embedded-class core with custom instruction set extension for DSP centric applications. Furthermore, the CORE-V MCU SoC comes with an FPGA prototyping flow for the widely used Digilent Genesys II board and a rich set of software development tools and toolchain support. Also, OpenHW will manufacture and make available our CORE-V MCU in Globalfoundries 22FDX together with an embedded FPGA from Quicklogic for custom logic such as accelerators. The CORE-V APU is built around the CORE-V CV64A6 a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA v2.3 as well as the draft privilege extension v1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. The CORE-V APU comes with an FPGA prototyping flow for the widely used Digilent Genesys II board and a rich set of software development tools, toolchain support and bootable Linux image.

Florian Zaruba is the OpenHW Group Director of Engineering, HW & SW Task Groups and a PhD student at the Integrated Systems Laboratory of ETH Zurich. His research interests include exploring new directions in energy-efficient high-performance computing. He is also the principle architect of CVA6 (Ariane). His experience includes a strong background in physical design with more than eight ASICs designed, manufactured and tested. Florian holds a Bachelor of Science degree from TU Wien and a master’s degree from ETH Zurich.

CORE-V Verif: Hands On

By Aimee Sutton (Metrics), Lee Moore (Imperas Software Ltd), Mike Thompson (OpenHW Group), Steve Richmond (Silicon Lab.), Greg Tumbush (EM Microelectronic).

The GitHub repository “core-v-verif” hosts the verification environment for the CORE-V family of RISC-V cores. The mandate of core-v-verif is to enable complete, measurable, end-to-end verification of the cores. Currently, there are three cores supported by core-v-verif with a forth to be added soon. Core-v-verif was used to complete the verification of the CV32E40P, an embedded class RISC-V core adopted from the PULP-Platform RI5CY project. In this session you will be introduced to the team that developed core-v-verif and get a sense of its architecture, implementation and capabilities. You may also be inspired to use “core-v-verif” as the verification environment for your RISC-V cores.

Aimee Sutton is a Corporate Applications Engineer and one of the original employees at Metrics. Prior to Metrics, she worked in design verification at small and large organizations, followed by over a decade in verification consulting. Aimee is passionate about helping DV teams improve their processes using best practices, novel innovations, and learnings from other industries. She is a vocal advocate for bringing cloud technology and a SaaS business model to the EDA industry. Aimee holds a Bachelor of Applied Sciences degree in Electrical Engineering from the University of Waterloo.

Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently developed PilotAware, a low-cost air traffic awareness device, helping aircraft to see and be seen./

Steve Richmond is the Design Verification Manager for the Central R&D Division of Silicon Labs, verifying advanced compute engines (AI/ML), processors, and accelerators. He is also the co-chair of the Verification Task Group at the OpenHW Group where he oversees verification methodology development and execution of verification for OpenHW cores, including the recent CV32E40P. Steve has over 20 years of design verification experience in networking, processors and mixed-signal designs.

Mike Thompson is the OpenHW Group Director of Engineering, Verification Task Group. He is a senior IC Functional Verification engineering manager with more than 20 years experience. Mike has led all aspects of the discipline with broad experience in simulation, emulation and prototyping plus management level experience of formal verification projects. He has both hands-on and management level experience with multiple SV/UVM projects and has developed teams driving SV/UVM for constrained-random, coverage driven verification efforts. Michael has been involved in a dozen successful tape-outs including five 100M gate-scale devices based on proprietary RISC processors which were verified using a novel random instruction generator and coverage model implemented in SV/VMM. Mike holds a Bachelor of Applied Science degree in Electrical and Electronics Engineering from the University of Regina, Canada.

Other bio TBA.

Panel – OpenHW IP Adopters

Moderated by Rick O'Connor (OpenHW Group).

Panelists: Sebastian Ahmed (Silicon Lab.), John Martin (EM Microelectronic), Robert Oshana (NXP), Tim Saxe (QuickLogic), Bertrand Tavernier (Thales Research & Technology).

This panel will explore the fast-growing, open source OpenHW ecosystem. OpenHW IP adopters will highlight the key drivers for their engagement in the OpenHW community. Panelists will share motivations for adopting the CORE-V Family of open-source RISC-V cores and will be available to take questions from the attendees.

Sebastian Ahmed is a silicon architect and technology leader with a specialty in energy-optimized designs spanning multimedia application processors, high-speed wireless networking, and MCUs. He is currently Senior Director of R&D and Lead HW Architect at Silicon Labs where he leads the internal machine-learning and compute platform development teams.

Robert Oshana is vice president of software engineering R&D for NXP Microcontrollers, where he leads open-source efforts across the company. In addition to being Chairman of the Board for the OpenHW Group, Rob is also a member of the RISC-V International board of directors. Rob is a recognized international speaker and a senior member of IEEE. He is also an adjunct professor at Southern Methodist University and the University of Texas.

Bios TBA.

OpenHW Project Execution

By Duncan Bees (OpenHW Group).

OpenHW uses a member-driven project framework to manage development across the CORE-V ecosystem: processor, software, hardware, and others. The framework incorporates the Eclipse open source flow, checkpoints needed for processor IP development, and agile teams. This session outlines the OpenHW approach to creating a full range of industry-quality technical outputs.

Duncan Bees is Director, Technical Programs of the OpenHW Group and the Eclipse Foundation. He manages the open-source engineering process supporting industrial-quality design and verification of the IP curated by the OpenHW Group, as well as the SW tools, FPGA, SoC implementations, and board level designs that support this ecosystem. Duncan has previously held executive roles with the Home Gateway Initiative (HGI) and the Digital Living Network Alliance (DLNA) and has contributed to many worldwide standards and technology initiatives. He managed R&D and product research for telecom, wireless and semiconductor companies. Duncan holds a bachelor’s degree in Applied Science from the University of British Columbia, a master’s degree with Honours in Electrical Engineering from McGill University, and has completed extensive study in machine learning, software, and data analytics. He is a certified Project Management Professional and Certified Scrum Master.

The OpenHW Day is organized by the OpenHW Group.

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