Spring 2022 RISC-V Week Banner

Registration is now open for on-site and online participation!

3 days on RISC-V and Open-Source Hardware!

Tuesday-Thursday, May 3-5, 2022 — CICSU, Campus Pierre et Marie Curie, Paris



The schedule and list of speakers of the RISC-V International Day is provided below.

Thursday, May 5

Time Speaker, Chair Title
08h30 Registration and distribution of badges.
09h00 Mark Himelstein State of the Union & the Road Ahead (slides)
09h30 Philipp Tomsich Driving Innovation: Evolving the Role of Software in the RISC-V Ecosystem Beyond Enablement (slides)
09h50 Philipp Tomsich and Mark Himelstein Maturing the RISC-V Ecosystem: From Technology to Product (slides)
10h15 Break – second poster session and exhibition are open
10h45 Johanna Baehr Open Source IC Design and Hardware Reverse Engineering Or: How I Learned to Stop Worrying and Love Reverse Engineering RISC-V Designs (slides)
11h05 Calista Redmond Global Importance, Adoption, and Opportunity for Europe in RISC-V (slides)
11h35 Florian Wohlrab RISC-V Goes Big (slides)
11h55 Andrew Dellow RISC-V : Securing the Future of Open Source Computing (slides)
12h20 Lunch – second poster session and exhibition are open
13h50 Jérôme Quévremont Introduction to RISC-V Functional Safety Special Interest Group (slides)
14h10 Perrine Peresse RISC-V IOMMU Architecture Overview (slides)
14h30 Olof Kindgren CPU is Only as Good as its Ecosystem: Turning RISC-V CPUs into Systems with FuseSoC (slides)
14h55 Break – second poster session and exhibition are open (last time for both)
15h25 Gary Martz Intel Investment to Help Deliver a Thriving RISC-V Ecosystem (slides)
15h45 John Davis Building an Open HPC Ecosystem (slides)
16h05 John Hartley RISC-V Compatible Processor IP by Syntacore (slides)
16h25 Michael Gielda Unlocking Open Source RISC-V SoC Verification (slides)
16h45 Calista Redmond and Christian Fabre Closing Remarks
17h00 End of the “RISC-V International Day” and of the “Spring 2022 RISC-V Week”

Presentations at the RISC-V International Day

State of the Union & the Road Ahead

By Mark Himelstein (RISC-V International). (slides).

This talk will summarize RISC-V International achievements for 2021 and provide a glimpse into our plans for 2022. Highlights include ISA and non-ISA efforts as well as how our organization had evolved to support our goals.

Mark Himelstein is the CTO for RISC-V International. Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing product architecture, analysis, mentoring and interim management. Previously, Mark co-founded Graphite Systems, Inc (acquired by EMC) where he was the VP of Engineering and CTO developing Big Data Appliances using massively parallel FLASH memory access. Prior to Graphite, Mark held positions as the CTO of Quantum Corp, Vice President of Solaris development engineering at Sun Microsystems and other technical management roles at Apple, Infoblox, Inc, and MIPS. Mark has a Bachelors degree of Computer Science and Mathematics from Wilkes University in Pennsylvania and a Masters degree in Computer Science from University of California Davis/Livermore. In addition to publishing numerous technical papers and holding many patents, he is the author of the book “100 Questions to Ask Your Software Organization”.

Driving Innovation: Evolving the Role of Software in the RISC-V Ecosystem Beyond Enablement

By Philipp Tomsich (VRULL GmbH). (slides).

The software efforts for RISC-V are quickly moving beyond the pure enablement of the existing architecture, as the focus shifts to a software-driven evolution of the architecture supported by first-class performance modelling and analysis tools.

This presentation introduces some key initiatives to create a robust ecosystem for ISVs while unlocking the benefits of RISC-V’s mix-and-match approach to ISA customisation: these range from efforts to rescue the fragmentation by standardising platforms to the standardisation of an unified discovery mechanism that allows the dynamic discovery of value-added or vendor-specific functionality. We can catch a glimpse of future directions of software-directed ISA evolution as seen in the areas of new synchronization instructions (Zawrs), matrix-multiplication, conditional branchless operations, performance modelling and performance analysis.

/Dr Philipp Tomsich is the Founder and Chief Technologist of VRULL GmbH, an engineering consultancy focused on engineering performance solutions through compiler optimizations, runtime performance tuning, system-level optimization, and hard-software co-engineering on the architectural and micro-architectural level. He supports the RISC-V mission as the Chair of the Software Horizontal Committee within RISC-V International, where he oversees the community involvement on Toolchains & Runtimes and drives the standardization effort for Platforms. Philipp brings broad experience and expertise in runtime systems (including Java VMs, compilers, operating systems kernels, and static code analysis), high-assurance applications, secure/trusted boot, and embedded hardware. His earlier contributions to open-source compilers have been focussed on ARMv8 and, more recently, on RISC-V. He has worked on languages and compilers for multi-core systems for over twenty years, being involved in engineering projects for high-assurance government applications. His previous career includes his role as the Founder and CTO of Theobroma Systems (a Software and Hardware engineering company offering tailored and standard modular solutions for high-assurance computing, which Cherry GmbH acquired in Oct 2020), compiler engineering at Silicon Graphics, and consulting in banking and government IT. He has held teaching and research roles at the Vienna University of Technology, where he also graduated with a degree and a doctorate in Computer Science, with the title M.Sc. (Dipl.-Ing.). In Austria, Philipp is a recognized court-certified expert on embedded systems, low-level programming, programming languages, compilers, and performance. He is an active contributor to open-source projects during his entire career, including the GNU toolchains (GCC, binutils, and glibc), OpenSSL, and as a custodian (i.e., global reviewer and maintainer) on the U-Boot project. He manages engineering teams working on the GNU toolchain, Linux kernel, cryptographic libraries, LLVM optimization, and Embedded Rust.

Maturing the RISC-V Ecosystem: From Technology to Product

By Philipp Tomsich (VRULL GmbH) and Mark Himelstein (RISC-V International). (slides).

RISC-V is quickly maturing to include solutions for embedded, datacenter, enterprise, automotive and mobile applications and are defining the use cases driving future innovation and increased adoption. The cost and flexibility of RISC-V to use a comprehensive set of instructions and customize the ISA extensions for implementers to deploy for individual markets and applications puts an emphasis on sharing between community members throughout a rapidly growing solution ecosystem without constraining the openness for customizations and innovation.

This presentation provides an overview of some existing software and ongoing key initiatives to enable adoption of RISC-V for ISVs, software distributions, and system vendors.

/Dr Philipp Tomsich is the Founder and Chief Technologist of VRULL GmbH, an engineering consultancy focused on engineering performance solutions through compiler optimizations, runtime performance tuning, system-level optimization, and hard-software co-engineering on the architectural and micro-architectural level. He supports the RISC-V mission as the Chair of the Software Horizontal Committee within RISC-V International, where he oversees the community involvement on Toolchains & Runtimes and drives the standardization effort for Platforms. Philipp brings broad experience and expertise in runtime systems (including Java VMs, compilers, operating systems kernels, and static code analysis), high-assurance applications, secure/trusted boot, and embedded hardware. His earlier contributions to open-source compilers have been focussed on ARMv8 and, more recently, on RISC-V. He has worked on languages and compilers for multi-core systems for over twenty years, being involved in engineering projects for high-assurance government applications. His previous career includes his role as the Founder and CTO of Theobroma Systems (a Software and Hardware engineering company offering tailored and standard modular solutions for high-assurance computing, which Cherry GmbH acquired in Oct 2020), compiler engineering at Silicon Graphics, and consulting in banking and government IT. He has held teaching and research roles at the Vienna University of Technology, where he also graduated with a degree and a doctorate in Computer Science, with the title M.Sc. (Dipl.-Ing.). In Austria, Philipp is a recognized court-certified expert on embedded systems, low-level programming, programming languages, compilers, and performance. He is an active contributor to open-source projects during his entire career, including the GNU toolchains (GCC, binutils, and glibc), OpenSSL, and as a custodian (i.e., global reviewer and maintainer) on the U-Boot project. He manages engineering teams working on the GNU toolchain, Linux kernel, cryptographic libraries, LLVM optimization, and Embedded Rust.

Mark Himelstein is the CTO for RISC-V International. Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing product architecture, analysis, mentoring and interim management. Previously, Mark co-founded Graphite Systems, Inc (acquired by EMC) where he was the VP of Engineering and CTO developing Big Data Appliances using massively parallel FLASH memory access. Prior to Graphite, Mark held positions as the CTO of Quantum Corp, Vice President of Solaris development engineering at Sun Microsystems and other technical management roles at Apple, Infoblox, Inc, and MIPS. Mark has a Bachelors degree of Computer Science and Mathematics from Wilkes University in Pennsylvania and a Masters degree in Computer Science from University of California Davis/Livermore. In addition to publishing numerous technical papers and holding many patents, he is the author of the book “100 Questions to Ask Your Software Organization”.

Open Source IC Design and Hardware Reverse Engineering Or: How I Learned to Stop Worrying and Love Reverse Engineering RISC-V Designs

By Johanna Baehr (TUM). (slides).

Open source hardware design is no longer only a dream of academia, but finally also embraced in larger corporations as a secure, verifiable and affordable solution to hardware design. However, from a hardware security point of view, allowing everyone to understand everything about your design is not always the most secure choice. In particular when it comes to attacks on hardware, giving away too much design information not only allows an attacker to understand your chip, but also to easily influence or manipulate your chip. This talk will outline the interaction between open source hardware design and hardware reverse engineering methods, identify where attacks on the design are made possible, and discuss opportunities to increase the security when manufacturing with open source hardware.

Johanna Baehr received her M.Sc degree in Electrical and Computer Engineering from the Technical University of Munich in 2016, and has since been working as a research assistant in the area of Chip Reverse Engineering. Her expertise includes all things reverse engineering, with a focus on netlist interpretation and abstraction. Her interests also include Reverse Engineering Countermeasures, Hardware Trojans Insertion and Detection, and Supply Chain Security and IC Trust.

Global Importance, Adoption, and Opportunity for Europe in RISC-V

By Calista Redmond (RISC-V International). (slides).

RISC-V adoption has accelerated across domains, from embedded to enterprise, from automotive to HPC. RISC-V has grown faster than any other architecture in history with both technical and business advantages. We’ve launched the new era of open computing as opportunities for custom microprocessors grow exponentially and barriers to innovation and markets are overcome through collaboration. Join me to hear about the success of RISC-V across industries, geographies, and stakeholders. We’ll take a look at community leaders ranging from multinationals to start-ups and the progress they’re making both independently and collaboratively. You’ll come away with an understanding of the technical advantages, business variables, and explosive opportunity that have compelled investment and engagement in the RISC-V community as we together drive commercialization and adoption of RISC-V everywhere.

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

RISC-V Goes BIG

By Florian Wohlrab (Andes Technology, RISC-V). (slides).

RISC-V is in the news daily, but will it be the ISA of the future? How does the commercial adoption look like? In this talk Andes Technology will share some insights about todays application using RISC-V already and why we are sure it will keep growing even more faster. We also will give a outlook on what a commercial CPU offering can look like including the EcoSystem. There will be mentioning about Linux capable MultiProcessor Systems, Vector powered number crunching and many more, make sure to join!

Florian Wohlrab is one of the first RISC-V Ambassadors and Head of Sales for EMEA and Japan at Andes Technology. His mission is to help bring RISC-V towards mainstream and enable others to easily get started within the RISC-V ecosystem. He is fascinated by the open, modular, compact and innovative RISC-V CPU designs. Before joining Andes Technologyhe worked in industrial PC and IoT fields, holding various technical and business roles within Europe and Asia.

RISC-V : Securing the Future of Open Source Computing

By Andrew Dellow (Huawei). (slides).

Security has often been a late consideration in the development of systems, hardware, and software. The emergence of exploits such as malware, trojans, the recent Spectre, Meltdown, RAMbleed attacks has resulted in serious financial and reputational losses. This illustrates the need to consider security as an essential component, directly built into a system rather than layered on top. RISC-V is a clean slate architecture with a unique opportunity to build in security as an intrinsic part of the hardware software and firmware.

This talk will describe the numerous initiatives and ongoing work to secure RISC-V and it’s ecosystem.

Andrew is Chief Security Architect at Huawei Technologies Research and Development UK, developing security architectures for Huawei’s Chipset business. Andrew has 20 years’ experience in system on chip security starting with the original development of robust Set Top Box SoCs for Pay TV, holding more than 40 patents in the area of SoC security. He is currently responsible for security strategy and architecture for device chipsets including IoT, TV, STB, IP Camera and connectivity chipsets. Andrew is the Chair of the RISC-V Security Horizontal Committee, helping to define the RISC-V security strategy and coordinating the many Technical and Special Interest Groups working on RISC-V security. Prior to joining Huawei in 2016, Andrew was a Distinguished Engineer and Technical Director at Broadcom Corp.

Introduction to RISC-V Functional Safety Special Interest Group

By Jérôme Quévremont (Thales). (slides).

Functional safety is aimed at controlling and minimizing the risk of systems catastrophic failures (i.e. failures that can injure or damage people’s health, equipment or the environment). In the context of software-driven applications, meeting functional safety requires that functional and timing correctness of applications is guaranteed throughout the system lifetime. The Functional Safety special interest group (SIG-Safety) gathers RISC-V International members from various critical domains (automotive, space, aerospace…) and different profiles (OEMs, hardware, software and service providers, researchers…) willing to promote functional safety needs in processors and identifying gaps that can be solved by RISC-V International specifications. This talk will introduce SIG-Safety and its activities to a broader audience.

Jérôme Quévremont graduated in telecommunications and electronics in 1995 (Télécom Bretagne, now IMT Atlantique). After developing telecom and security integrated circuits at Texas Instruments and Thales Communications, in 2007 he headed a development lab, specialized in specifying, developing and validating secure- and crypto-chips in ASIC and FPGA technologies. His main expertise is related to ASICs and systems-on-chip in the field of networks, radio, cryptography, hardware-reconfigurable platforms, multi-cores and trusted computing. In March 2020, he joined Thales Research & Technology as an architect and a project leader in the field of RISC-V and open hardware, with special interest on embedded efficient computing, functional safety and security. Jérôme has been the chair of the Functional Safety special interest group at RISC-V International since 2020. At the OpenHW Group open-source organization, he holds the position of Technical WG, vice-chair Cores TG, technical project leader for CVA6 (a RISC-V application core).

RISC-V IOMMU Architecture Overview

By Perrine Peresse (SiFive). (slides).

The Input-Output Memory Management Unit (IOMMU) is an essential component in between an IO device and a memory controller that translates device virtual addresses into physical addresses. This talk will introduce the IOMMU Task Group’s charter. It will then describe the IOMMU usage models in a SoC and provide an overview of the initial version of the IOMMU architecture. The presentation will end with the task group status and future challenges.

Perrine Peresse is a Senior Principal Architect at SiFive with 20 years of industry experience. She contributed to the architecture of multiple ARM based SoCs for a broad range of application areas from SBSA compliant server SoC to storage and networking SoCs . She was also a micro-architect in charge of a several IPs such as a queuing and scheduling central engine which handled ethernet ports with inline classifier and offload engines. She is currently the architect of the IOMMU within SiFive and the vice-chair of the RISC-V IOMMU TG.

A CPU is Only as Good as its Ecosystem: Turning RISC-V CPUs into Systems with FuseSoC

By Olof Kindgren (Qamcom Technology AB). (slides).

A great 20th century thinkers once said "A CPU is only as good as its ecosystem". RISC-V provides us with a CPU but how can we turn that into systems more efficiently? The award-winning FuseSoC provides us with a tool for managing IP cores and combining them to create larger systems.

Being the most popular package manager for IP cores, there are already hundreds of FuseSoC-compatible cores available. Most high-profile open source silicon projects have already adopted FuseSoC or are looking at doing so, and it is being increasingly used for development of proprietary systems as well. With support for more than 30 different EDA tool flows it covers a wide range of work flows from synthesis to simulation to formal verification.

Sounds great, doesn't it? It sure does, and this presentation will take you through the basics of FuseSoC to help you get started and look at how FuseSoC can help you focus on your core business instead of your cores.

The award-winning Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the award-winning FuseSoc IP core package manager; the award-winning SERV RISC-V CPU and SweRVolf, a reference platform for the SweRV CPU family. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike. In recent years he is also involved in the RVFPGA computer architecture course and serve as a RISC-V ambassador

Intel Investment to Help Deliver a Thriving RISC-V Ecosystem

By Gary Martz (Intel). (slides).

RISC-V is poised to become the next major compute solution. There is tremendous momentum and the community of RISC-V developers is off to a great start. Intel is excited to join this community and share our plans to invest in the technologies and partnerships to help RISC-V achieve commercial success.

Gary Martz is Senior Director Intel Foundry Services, RISC-V Ecosystem Enablement, at Intel.

Building an Open HPC Ecosystem

By John Davis (BSC). (slides).

Over that last 3 decades, we have witnessed a transition from closed software ecosystems being the foundation for HPC, enterprise, and business to open source software ecosystems based on Linux and other software in the stack. The combination of current technology trends, the slowing of Moore’s Law, and cost prohibitive silicon manufacturing inhibit significant power-performance gains by relying on traditional closed ecosystems, especially in HPC, technology pushed to the extreme. This new regime forces systems to be much more specialized to achieve the power-performance profiles required for a supercomputer. In the past, HPC has led the way forward, defining the bleeding edge of technology. HPC can do this again with open hardware, as it has done in software with adopting Linux and open source in general. The RISC-V ISA provides the open standard in HW to enable this open HPC ecosystem. Much like Arm, RISC-V can follow the same, now accelerated path from embedded/IoT to HPC. The RISC-V Special Interest Group for HPC is helping to define and build this ecosystem. This talk will highlight the SIG HPC efforts and some of the European R&D efforts making RISC-V the future platform for HPC.

John Davis Dr. John D. Davis is the Director of the Laboratory for Open Computer Architecture at Barcelona Supercomputing Center (BSC). He has published over 30 refereed conference and journal papers in Computer Architecture (ASIC and FPGA-based domain-specific accelerators, non-volatile memories and processor design), Distributed Systems, and Bioinformatics. He also holds over 35 issued or pending patents in the USA and Europe. He has designed and built distributed storage systems in research and as products. John has led the entire product strategy, roadmap, and execution for a big data and analytics company. He has worked in research at Microsoft Research, where he also co-advised 4 PhDs, as well as contributed to large and small start-up companies. John holds a B.S. in Computer Science and Engineering from the University of Washington. He also holds a M.S. and Ph.D. in Electrical Engineering from Stanford University. At BSC, John is leading the MEEP project and is the technical leader of the eProcesor project and the European PILOT project. He also leads several industrial research collaborations, all centered around a full open source ecosystem from software down to hardware, open source processors and accelerators. John is the founder and chair of the RISC-V Special Interest Group on High Performance Computing (SIG-HPC).

RISC-V Compatible Processor IP by Syntacore

By John Hartley (Syntacore). (slides).

An introduction to designing with silicon proven, highly configurable and extensible, best-in-class RISC-V open-source 32 and 64 bit cores.

Mr. Hartley has over 28 years of experience in the semiconductor industry, having held senior sales and marketing positions in Europe, Asia and the Americas at companies such as Microchip, Tundra Semiconductor (now IDT), PLX (now Broadcom) and UltraSoC (now Siemens Mentor). Most recently, Mr. Hartley held the position of Chief Commercial Officer at Agile Analog, a Cambridge based Analog IP company. He is currently Chief Commercial Officer at Syntacore.

Unlocking Open Source RISC-V SoC Verification

By Michael Gielda (Antmicro). (slides).

While RISC-V has spawned a large number of open source core implementations and energized the open hardware and design tooling community, verification - a major element of any modern SoC design - is still primarily done with proprietary tooling, which prevents the collaborative approach to development we have seen in other areas. CHIPS Alliance takes the RISC-V mission beyond the CPU and into the SoC and tooling domains, and one of our key focus areas has been open source verification using Verilator. The effort, spearheaded by Antmicro, Western Digital and Google, has seen very good progress in the recent months. We will discuss the current capabilities, opportunities and the road ahead for this effort, including dynamic scheduling which is on the way to being merged into Verilator in the upcoming 5.X version, the UHDM SystemVerilog frontend as well as plans for supporting further SystemVerilog constructs and other HDL languages.

Michael Gielda is VP Business Development at Antmicro, Chair of Outreach for CHIPS Alliance and a Chair of Marketing for the Zephyr Project. He is involved in many open source software and hardware projects related to software-driven tools and methodologies, AI, FPGA & ASIC development.

Closing Remarks

By Calista Redmond (RISC-V International) and Christian Fabre (CEA, IRT-Nanoelec).

Closing remarks on the “RISC-V International Day” and the “Spring 2022 RISC-V Week”. See you soon!

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

Christian Fabre is Senior Research Engineer in the digital architecture and IC design department in the research technology division of CEA. He is currently part of the team working on EPI's VaRiable eXtended Precision (VRP/VXP) RISC-V accelerator that operates on floating-point numbers with up to 512 bits of significand and 18 bits of exponent. His background is in compilation, operating system, and object-oriented UML modeling. He is the General Chair of the “RISC-V Week” series of conferences.

 

The organizers of the RISC-V International Day are

 
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