Spring 2022 RISC-V Week Banner

Registration is now open for on-site and online participation!

3 days on RISC-V and Open-Source Hardware!

Tuesday-Thursday, May 3-5, 2022 — CICSU, Campus Pierre et Marie Curie, Paris



The program of the “4th RISC-V Meeting” is dispatched over two days:

This great program was possible thanks to our organisers and sponsors.

Tuesday, May 3

Time Speaker, Chair Title
08h00 Registration and distribution of badges.
09h00 Fabien Clermidy Welcome Address from the IRT NanoElec
09h15 Christian Fabre Overview of the “Spring 2022 RISC-V Week” and “4th RISC-V Meeting”
09h25 Kevin Martin Introduction to the posters sessions (slides)
09h30 Frédéric Pétrot Tutorial host
09h30 Alistair Francis Free RISC-V Systems: Benefits and Status of QEMU
10h15 Break – exhibition and first poster session are open
10h45 Teresa Cervero Session on the RISC-V Software Stack
10h45 Nick Kossifidis Demystifying the RISC-V Linux software stack (slides)
11h30 Roger Ferrer SW Toolchain for RISC-V Vector Extensions (slides)
11h50 Teresa Cervero Panel with Nick and Roger on the RISC-V Software Stack
12h00 Marion Andrillat Session on the exhibition
12h00 Introduction of the booths of OpenHW Group (slides), SiFive (slides), Codasip (slides), Andes Technology (slides), Siemens (slides), RISC-V International (slides), and CEA (slides)
12h30 Lunch – exhibition and first poster session are open
14h00 Jérôme Quévremont Session on RISC-V in practice
14h00 Michael Gielda and Adam Jesionowski Springbok: Using Renode and IREE to prototype and develop ML models on RVV (slides)
14h30 Mathieu Jan Formal Processor Modeling for Analyzing Safety and Security Properties on RISC-V case studies (slides)
14h45 Borja Pérez Coyote: an open-source simulator for HPC architectures (slides)
15h00 Andrea Bartolini RISC-V based Power Management Unit for an HPC processor
15h30 Jérôme Quévremont Panel with Michael, Mathieu, Borja, and Andrea on RISC-V in practice
15h45 Break – exhibition and first poster session are open
16h15 Maxime Pelcat Session on EDA tools
16h15 Jean-Roch Coulon Verification of the CVA6 Open-Source Core
16h45 Jan Kuper Digital hardware design with Clash (slides)
17h15 Luca Carloni Open-Source Hardware for Heterogeneous Computing with ESP and RISC-V
17h45 Maxime Pelcat Panel with Jean-Roch, Jan, and Luca on EDA tools
18h00 End of 1st day of the “4th RISC-V Meeting”

Wednesday, May 4

Time Speaker, Chair Title
08h30 Registration and distribution of badges.
09h00 Olivier Sentieys Keynote Host
09h00 Rick O'Connor Open-Source HW Commercial Adoption: Lessons Learned (slides)
09h45 Sébastien Pillement and Jérôme Quévremont French RISC-V Student Contest: Lessons Learned
10h00 Break – first poster session (last time) and exhibition are open
10h30 Romain Dolbeau Session on the European Processor Initiative (EPI)
10h30 Jesús Labarta The Accelerator Tile of European Processor Initiative
11h00 Francesco Minervini Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing
11h15 Matheus Cavalcante The RISC-V based Stencil Tensor Accelerator of EPI (slides)
11h30 César Fuguet Tortolero VRP/VXP: VaRiable eXtended Precision RISC-V Accelerator for High-Precision
11h45 Romain Dolbeau Panel with Jesús, Francesco, Matheus and César on the EPI
12h00 Lunch – second poster session and exhibition are open
13h30 John Davis Session on RISC-V computing cores
13h30 Olof Kindren How much score could a CoreScore score if a CoreScore could score cores? (slides)
13h50 Roger Espasa Atrevido: SemiDynamics Out-of-Order RISC-V Core
14h10 Charles Papon NaxRiscv: An open-source OoO superscalar softcore (slides)
14h25 Zdeněk Přikryl Customizing RISC-V designs to unlock innovation with Codasip (slides)
14h40 Davide Schiavone OpenHW CORE-V Roadmap (slides)
14h55 Jérôme Quévremont An Open-Source Application Core: CVA6 from the OpenHW Group
15h10 John Davis Panel with Olof, Roger, Charles, Davide and Jérôme on RISC-V computing cores
15h45 Break – second poster session and exhibition are open
16h00 Olivier Savry Session on CHERI
16h00 Simon W. Moore Intro to CHERI capability-based memory protection (slides)
16h30 Jonathan Woodruff The CHERI-RISC-V experimental extension (slides)
16h45 Peter Rugg Four CHERI RISC-V micro-architectures (slides)
17h00 Alex Richardson Software Ecosystem: QEMU, LLVM, CheriBSD (slides)
17h15 Franz Fuchs Demo: Detecting and Resolving an Exploit under CheriBSD on a Multi-core, Superscalar Softcore (slides)
17h30 Olivier Savry Panel with Simon, Jonhathan, Peter, Alex and Franz on CHERI.
18h00 Christian Fabre Session on more fun to come at the “Spring 2022 RISC-V Week”!
18h00 Calista Redmond Introduction and program of the “RISC-V International Day”
18h10 Christian Fabre Closing remarks for the “4th RISC-V Meeting”, and timing and directions to the diner cruise (slides)
18h15 End of 2nd and last day of the “4th RISC-V Meeting”

Speakers of Tuesday May 3

Welcome Address from the IRT Nanoelec

By Fabien Clermidy (CEA, Nanoelec, a French Technological Research institute).

The Nanoelec Technological Research Institute (IRT Nanoelec) is a consortium of private and public sector players based in Grenoble that help companies create value and enable their products to stand out on the digital transition stage. This talk will present its organisation, activities and research areas.

Fabien Clermidy is currently heading the digital architecture and IC design department in the research technology division of CEA. In this position, he develops the hardware and software computing strategy for High-Performance Computing, Artificial Intelligence, Cybersecurity and Cyber-Physical-Systems in relation with system developments in automotive, factory of future, avionics or defense and new nanotechnologies such as 3D chip-stacking, embedded Non-Volatile-Memories, photonic and quantum computing. Fabien has been working in CEA since 2000, holding different positions as project leader and manager of different teams. He is also a senior expert with a Ph’D supervisor degree and has published more than 80 papers in the greatest conferences such as ISSCC or DAC.

Overview of the “Spring 2022 RISC-V Week” and “4th RISC-V Meeting”

By Christian Fabre (CEA, IRT-Nanoelec).

This presentation will provide a quick overview of the “Spring 2022 RISC-V Week” and its first event, the “4th RISC-V Meeting”.

Christian Fabre is Senior Research Engineer in the digital architecture and IC design department in the research technology division of CEA. He is currently part of the team working on EPI's VaRiable eXtended Precision (VRP/VXP) RISC-V accelerator that operates on floating-point numbers with up to 512 bits of significand and 18 bits of exponent. His background is in compilation, operating system, and object-oriented UML modeling. He is the General Chair of the RISC-V Weeks series of conferences.

Introduction to the posters sessions

By Kevin Martin (Univ. Bretagne-Sud, Lab-STICC). (slides).

This presentation will discuss the first Call for Posters of the “RISC-V Week” series and its outcome, the two poster sessions displayed during the “Spring 2022 RISC-V Week”.

Kevin Martin is Associate professor at University Bretagne-Sud.

Free RISC-V Systems: Benefits and Status of QEMU

By Alistair Francis (Western Digital).

QEMU is an open source emulator that supports the RISC-V ISA. QEMU is extremely quick and provides a vast range of advanced features for users and developers. QEMU has been used in the past for software development, but as hardware become more available is it still as beneficial? This talk will present an introduction to QEMU and how it works. It will then describe how useful QEMU can be for developing for RISC-V, even as more hardware becomes available. This will include details about the current mainline status for QEMU, including vendor and draft extension support. It will also discuss the value of developing extensions using QEMU. The presentation can then end with some demonstrations and examples of using QEMU for RISC-V development.

Alistair Francis currently works at Western Digital as part of the RISC-V software research team. He is the QEMU RISC-V maintainer; developing, reviewing and merging QEMU patches. He also has a focus on security, specifically secure operating systems related to Root of Trust (RoT) devices. He is the vice-chair of the RISC-V Security Response Team. He is actively working on supporting Tock and the Tock ecosystem on the OpenTitan platform. He also contributes to and maintains a range of different software projects, from low level operating systems to high level system applications. He has contributed to glibc, strace, OpeOCD, Oreboot, OpenEmbedded, Linux, Xvisor, OpenSBI, seL4, SweRV-ISS, Open Compute Project security specifications and a variety of other projects.

Demystifying the RISC-V Linux software stack

By Nick Kossifidis (FORTH/CARV). (slides).

In the past few years since the initial RISC-V Linux port got merged in upstream Linux, multiple contributors from various companies and institutions have worked towards improving the code, supporting more features, and the new ISA extensions introduced by RISC-V International. Supporting an architecture as modular as RISC-V, while also keeping track of relevant kernel updates and the rest of the system software stack can be a real challenge. In this talk we 'll try to demystify the RISC-V system software stack by providing an overview of the various elements and how the interact with each other, and provide an overview of the development process of the RISC-V Linux port. We'll focus on key kernel features that are currently supported, ongoing work on new features, and share our experience on contributing to the RISC-V system software stack as part of our work on the European Processor Initiative (EPI).

Nick Kossifidis is a principal research engineer at the FORTH research center in Greece (at the CARV laboratory of the Institute of Computer Science), with extensive experience in networking, systems software, and security. He has worked as an IT security consultant and penetration tester for Fortune 500 companies on high profile projects, and is an active contributor on security and software related topics within the RISC-V technical committee and the RISC-V community in general. He is the current Chair of the RISC-V TEE TG, and recipient of a RISC-V 2021 Ratification award (on behalf of the TEE TG) and a RISC-V 2021 outstanding community contributor award. Nick has multiple contributions in open source projects, including various subsystems of the Linux kernel, and is currently working on the bringup, validation, and optimization process of various RISC-V prototypes of the European Processor Initiative (EPI).

SW Toolchain for RISC-V Vector Extensions

By Roger Ferrer (BSC). (slides).

The RISC-V Vector Extension (RVV) provides vector capabilities to the RISC-V ecosystem. It does this by providing a very flexible and rich ISA which features vector length and masking support. This flexibility comes with some challenges in implementing it in compilers. In this talk we will see how we tackled these issues in the context of the EPI project, which ideas were ultimately implemented in upstream LLVM and which didn't. With code generation well understood now, the focus shifts on how to make good use of the extension in the compiler via vectorization. We will see the ongoing work in the LLVM Loop Vectorizer, what is there and what is still missing.

Roger Ferrer Ibanez is a research engineer at the Barcelona Supercomputing Center (BSC) who works on compilers. In the past he worked in enabling the parallel programming research in task based models at BSC. While he is still participating on this, these days most of his work revolves about enabling support for the RISC-V vector extension in LLVM in the context of the EPI, MEEP and EUPILOT projects.

Springbok: Using Renode and IREE to prototype and develop ML models on RVV

By Michael Gielda (Antmicro) and Adam Jesionowski (Google). (slides).

Efficient ML development for low-power applications requires a tight control of the entire hardware/software/ML stack. To rapidly prototype different approaches, a simulation based workflow is very useful to explore tradeoffs and observe the behavior of the target (virtual) hardware. This talk will present an end-to-end flow for generating RISC-V Vector Extension (RVV)-based accelerators using the IREE machine learning library and testing them in the open source Renode simulation framework.

Michael Gielda is VP Business Development at Antmicro, Chair of Outreach for CHIPS Alliance and a Chair of Marketing for the Zephyr Project. He is involved in many open source software and hardware projects related to software-driven tools and methodologies, AI, FPGA & ASIC development.

Adam Jesionowski has worked in embedded systems since graduating from Rose Hulman Institute of Technology in 2010. Currently he works at Google Research, developing devices for low power ambient machine learning.

Formal Processor Modeling for Analyzing Safety and Security Properties on RISC-V case studies

By Mathieu Jan (CEA). (slides).

The emergence of open hardware initiatives, for instance based on the RISC-V ISA, exposes more easily the exact behavior of hardware designs. They can then be analyzed and combined with application-level semantics to formally verify complex safety and security properties at system level, in particular by integrating non-functional characteristics such as timing. This is the goal of the the LEAF approach developped at CEA, which currently focuses, on one hand, on timing predictability & memory contention evaluations required by safety-critical systems, and on the other hand on assessments of fault-injection attacks over secured embedded systems. In this talk, we first briefly present an overview of LEAF. Then, we focus on our current results over several RISC-V case studies for: 1) fault-injection assessment, i.e. the CV32E40P processor from the OpenHW Group, and 2) the automatic construction of pipeline datapaths from high-level HDL code (RISC-V mini, Sodor, KyogenRV, Rocket).

Dr Mathieu Jan obtained his engineer diploma in 2003 and got a PhD in 2006 on the subject of management of data on grid architectures in an INRIA laboratory (Rennes). He joined the laboratory of Embedded Real-Time Systems Laboratory at “Commissariat à l’Energie Atomique” (the French DoE) in 2007. His main research interests are around real-time and embedded systems (network on chip, scheduling, mapping, low-power, formal modeling and verification). He is senior expert on these subjects at CEA Tech since 2014, he obtained an Habilitation à Diriger des Recherche (HDR) in 2016 and is a CEA Research Director since 2021. He is member of the various program committees, such as the International Real-Time and Network Systems (RTNS) conference, has co-advised 5 PhD thesis and is the director of 4 on-going PhD thesis. He spent the whole year 2019 as visiting scholar at the University of California, Berkeley (UCB) in the group of Prof. Edward Lee. Since 2020 Mathieu is leading a research team on the hardware/software formal verification of CPS systems.

Coyote: an open-source simulator for HPC architectures

By Borja Pérez (BSC). (slides).

High core counts and complex memory hierarchies are typically the staple of HPC architectures. This is often synonym to long delays and high implementation efforts when trying to make overall decisions regarding the flavor of a new architecture. This talk introduces Coyote, an open-source, execution-driven simulator based on Spike and Sparta, with a focus on the movement of data throughtout the modeled system. This focus strikes a balance between fidelity and simulation throughput, enabling reasoning on the RISC-V based HPC architectures of tomorrow.

Borja Pérez received his degree in Computer Science and Engineering and his PhD in Science and Technology from Universidad de Cantabria. He has since led the performance modeling efforts in the MEEP (Marenostrum Experimental Exascale Platform) in BSC. His main research interests include simulation, heterogeneous systems, caching and parallelism.

RISC-V based Power Management Unit for an HPC processor

By Andrea Bartolini (Università di Bologna) and Alessandro Ottaviano (ETHZ).

High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems, which require Power Controller Subsystems (PCS) to provide advanced multi-input, multi-output (MIMO) dynamic control of operating points to meet energy, power and thermal constraints. In the European Processor Initiative (EPI), a PCS IP has been designed to extend the PULP platform to comply with the industrial standards adopted in the HPC segment for on-chip, off-chip power management. The SoC is named ControlPULP and features a fully-digital and highly capable RISC-V based parallel microcontroller IP optimized for power management of complex HPC processors. Its design supports a manager core and peripherals paired with a cluster of 8 processors to accelerate the Power Control Firmware workload, Direct Memory Access (DMA) engine for accessing on-chip sensors, a uDMA engine for off-chip AVSBUS/PMBUS peripheral support and BMC-based communication through the Management Component Transport Protocol (MCTP). The controller implements basic System Control and Management Interface (SCMI) doorbell-based protocol hosting up to 144 external interrupt lines. On the software side, it relies on an open-source Real-time Operating System (FreeRTOS) for agile scheduling of the underlying Control Policy and interface handling. The presentation will describe the power management problem, requirements, and the ControlPULP design and performance.

Andrea Bartolini holds an assistant professor (RTD-B) position with the Department of Electrical, Electronic and Information Engineering (Guglielmo Marconi) at the University of Bologna. He was a postdoctoral researcher with Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich. He has authored or co-authored more than 120 papers in peer-reviewed international journals and conferences and several book chapters with a focus on dynamic resource management-ranging from embedded to large scale HPC systems. He has collaborated with several international researchers and companies. Andrea Bartolini has been the main responsible for the design of advanced power management and monitoring support on the first Cavium ThunderX cluster, the D.A.V.I.D.E. and Marconi100 supercomputers. Since 2018 Andrea Bartolini has served as the technical leader for the European Processor Initiative (EPI) power management design.

Alessandro Ottaviano received the B.Sc. from Politecnico di Torino, Italy, and the M.Sc. as a joint degree between Politecnico di Torino, Grenoble INP-Phelma and EPFL Lausanne, in 2018 and 2020 respectively. Since 2021, he has been a Research Assistant with the Integrated Systems Laboratory, ETHZ in Zürich. His research interests include real-time and predictable computing systems and energy-efficient processor architectures.

Verification of the CVA6 Open-Source Core

By Jean-Roch Coulon (Thales).

Unusual: for one of the first times, an open-source instruction set architecture, RISC-V, is implemented in many different processors. How to leverage this for verification? This is Thales challenge within OpenHW Group. This is an opportunity to share design verification plans, test benches, reference models, UVM agents, random test generator and continuous integration. And also to reuse related open-source projects like riscv-arch-test, riscv-tests, Spike, Verilator, and riscv-dv. This tutorial presents the challenges and solutions to verify the CVA6 open-source core.

Jean-Roch Coulon is RISC-V Architect at Thales group in France, he designed processors to add security in ARM, SPARC, proprietary and now RISC-V implementations. Expert in processor, toolchain, security, cryptography or code size density. His main contributions in RISC-V are the 32bits version of CVA6 (CV32A6), CV-X-IF implementation and verification. He is an OpenHW group committer; developing, reviewing and merging CVA6 and CORE-V-VERIF pull requests.

Digital hardware design with Clash

By Jan Kuper (QBayLogic). (slides).

Clash is a system for digital architecture design (FPGA, ASIC), which generates traditional HDL (VHDL, Verilog) from a high level, functional specification written in Haskell. A design can be fully developed and tested in software, while at the same time offering full control over detailed hardware issues. It has several features, such as higher order functions, domain specific embedded languages, polymorphism. In particular the typing system is very helpful in verification, including time domain crossings and synchronization. Last but not least, a design process in Clash is fundamentally model based, meaning that all design steps, starting from an initial model, are expressed in the same language, and the correctness of each step is provable. During the talk we will illustrate some of these aspects by examples.

Jan Kuper studied mathematics and logic, and holds a PhD in the foundations of mathematics and computer science. For more than 30 years he worked at the University of Twente in the fields of logic, functional programming, and embedded systems. His research led to the development of Clash, and in 2016 he founded (together with Christiaan Baaij) the company QBayLogic which offers services in FPGA design using Clash.

Open-Source Hardware for Heterogeneous Computing with ESP and RISC-V

By Luca Carloni (Columbia University).

System-on-chip (SoC) architectures are increasingly heterogeneous, as they feature multiple general-purpose processor cores with many specialized hardware accelerators. The complexity of SoC design threatens to widen the gap between the capabilities provided by semiconductor technologies and the productivity of computer engineers. Open-source hardware is a promising avenue to address this challenge by enabling design reuse and collaboration. ESP is an open-source research platform for SoC design that combines a scalable tile-based architecture and a flexible system-level design methodology. With ESP, designers can rapidly prototype an SoC architecture with multiple RISC-V processor cores and dozens of loosely-coupled accelerators, all interconnected with a multiplane network-on-chip. The ESP methodology promotes system-level design while accommodating different specification languages and design flows. Conceived as a heterogeneous system integration platform, ESP is intrinsically suited to foster collaborative engineering across the open-source hardware community.

Luca Carloni is Professor and chair of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree Summa cum Laude in Electronics Engineering from the University of Bologna, Italy, and the MS and PhD degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley. His research interests include heterogeneous computing, system-on-chip platforms, and embedded systems. He coauthored over one hundred and seventy refereed papers. Luca received the NSF CAREER Award, the Alfred P. Sloan Research Fellowship, and the ONR Young Investigator Award. He is an IEEE Fellow.

Speakers of Wednesday May 4

Open-Source HW Commercial Adoption: Lessons Learned

By Rick O'Connor (OpenHW Group). (slides).

This talk will provide a brief overview of Open-Source HW activity across the industry, barriers to adoption of Open-Source HW and challenges associated with SoC design. Lessons learned related to the OpenHW Group Governance model and adoption of CORE-V Family of open source RISC-V cores will also be presented. The CORE-V family is an OpenHW Group project to develop, deploy, and execute pre-silicon functional verification and SoC based development kits of the CORE-V family of open-source RISC-V cores. Written in SystemVerilog, CORE-V open-source IP cores match the quality of IP offered by established commercial providers and are verified with state-of-the-art, auditable flows.

Rick O'Connor is Founder, President & CEO of the OpenHW Group a not-for-profit, global organization driven by its members and individual contributors where HW and SW designers collaborate in the development of open-source cores, related IP, tools and SW such as the CORE-V Family of open- source RISC-V cores. Previously Rick was Executive Director of the RISC-V Foundation which was launched by Rick in 2015. Today, under RISC-V International, the RISC-V ecosystem consists of more than 400 members building an open, collaborative community of software and hardware innovators powering processor innovation. With many years of Executive level management experience in semiconductor and systems companies, Rick possesses a unique combination of business and technical skills and over Rick’s career, he was responsible for the development of dozens of products accounting for over $750 million in revenue. Rick holds an Executive MBA degree from the University of Ottawa, Canada and is an honors graduate of the faculty of Electronics Engineering Technology at Algonquin College, Canada.

French RISC-V Student Contest: Lessons Learned

By Sébastien Pillement (GDR SOC2, Nantes Université) and Jérôme Quévremont (Thales).

In France, Thales, GDR SOC2 and CNFM are currently running the second season of a contest for master’s students where they have to optimize the OpenHW Group’s CVA6 open-source RISC-V core. If last year they had to optimize the overall, performance of the core for some benchmarks, this year the main goal is to increase its energy efficiency when running an AI application. Twelve teams from different universities have applied for the competition that runs over six months and can be integrated in the education curriculum. In this talk, the organizers will explore the lessons learned from the previous season contest and the impact on the academic community.

Sébastien Pillement is full Professor in Polytech'Nantes, France since 2012. He was an associate professor at IUT in Lannion, the subdivision of the University of Rennes 1, during 13 years. He is currently a research member of the ASIC Research Team of the IETR Lab. (Research Institute in Electronic and Telecommunication). He received a Ph.D. degree and Habilitation degrees in Computer Science from the University of Montpellier II and the University of Rennes 1 respectively. His research interests include dynamically reconfigurable architectures, system on chips, design methodology and NoC (Network on Chip) based circuits. He focuses his research on designing flexible and efficient architectures managed in real-time and on the use of these architectures to increase the reliability of systems. He his currently deputy director go the GDR SOC2 (a research group of French labs) and of IETR.

Jérôme Quévremont graduated in telecommunications and electronics in 1995 (Télécom Bretagne, now IMT Atlantique). After developing telecom and security integrated circuits at Texas Instruments and Thales Communications, in 2007 he headed a development lab, specialized in specifying, developing and validating secure- and crypto-chips in ASIC and FPGA technologies. His main expertise is related to ASICs and systems-on-chip in the field of networks, radio, cryptography, hardware-reconfigurable platforms, multi-cores and trusted computing. In March 2020, he joined Thales Research & Technology as an architect and a project leader in the field of RISC-V and open hardware, with special interest on embedded efficient computing, functional safety and security. Jérôme has been the chair of the Functional Safety special interest group at RISC-V International since 2020. At the OpenHW Group open-source organization, he holds the position of Technical WG, vice-chair Cores TG, technical project leader for CVA6 (a RISC-V application core).

The Accelerator Tile of European Processor Initiative

By Jesus Labarta (BSC).

The European Processor Initiative (EPI) project aims at developing European processor technology for High Performance Computing (HPC) and emerging application areas. An important objective of the project is to develop a fully owned implementation of accelerators based on RISC-V cores. The resulting EPAC architecture integrates generic RISC-V vector cores plus other more specialized accelerator component (STX) also based on RISC-V targeting AI and stencil kernels acceleration plus a RISC-V processor (VRP) with support for variable and high precision arithmetic.

The talk will introduce the fundamental vision behind the design and the overall resulting architecture. The project has produced a test chip in GF 22 nm technology, featuring 4 vector cores, 2 STX clusters and one VRP processor. In parallel, an FPGA implementation of the vector core and memory subsystem has been implemented to be used as a software development vehicle (SDV), continuous integration (CI) and co-design support infrastructure. This system runs as stand alone self hosted Linux node where general purpose application from the HPC but also other domains can be run. I will report some initial results of these evaluations and comparisons to other state of the art architectures.

Prof. Jesús Labarta received his Ph.D. in Telecommunications Engineering from Universitat Politècnica de Barcelona (UPC) in 1983, where he has been a full professor of Computer Architecture since 1990. He was Director of European Center of Parallelism at Barcelona from 1996 to the creation of BSC in 2005, where he is the Director of the Computer Sciences Dept. His research team has developed performance analysis and prediction tools and pioneering research on how to increase the intelligence embedded in these performance tools. He has also led the development of OmpSs and influenced the task based extension in the OpenMP standard. He has led the BSC cooperation with many IT companies. He is now responsible of the POP center of excellence providing performance assessments to parallel code developers throughout the EU and leads the RISC-V vector accelerator within the EPI project. He has pioneered the use of Artificial Intelligence in performance tools and will promote their use in POP, as well as the AI-centric co-designing of architectures and runtime systems. He was awarded the 2017 Ken Kennedy Award for his seminal contributions to programming models and performance analysis tools for high performance computing, being the First Non US Researcher receiving it.

Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing

By Francesco Minervini (BSC).

The availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores. This talk presents Vitruvius, the first RISC-V vector accelerator developed at BSC for the Supercomputing domain, as part of the EPI project. Vitruvius implements the RISC-V vector extension specification V0.7.1. and can be easily connected to a scalar core using the Open Vector Interface (OVI) standard in a plug-and-play fashion. Vitruvius natively supports long vectors: 256 Double Precision (DP) floating-point elements in a single vector instruction. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File (VRF) and functional units (one integer, one floating-point). It adopts a novel hybrid in-order/out-of-order execution scheme, supported by vector register renaming and arithmetic/memory instruction decoupling. When configured with eight vector lanes, Vitruvius reaches a maximum frequency of 1.25 GHz when synthesized using GLOBALFOUNDRIES 22FDX FD-SOI. The silicon implementation has a total area of 1.13 mm2 and total estimated power around 1W.

Francesco Minervini received the MSc. and the BSc. from the University of Rome "La Sapienza" in 2018 and 2015, respectively. He has been working as an RTL Research Engineer for BSC for three years, as the main designer of the EPI Vector Accelerator. He's also a PhD student at the Polytechnic University of Catalonia (UPC). His main interests are on vector architectures, reconfigurable interconnects and multi-core systems.

The RISC-V based Stencil Tensor Accelerator of EPI

By Matheus Cavalcante (ETHZ). (slides).

In this talk we will explain the Stencil and Tensil Accelerator Unit (STX) that is part of the EPI accelerator. The design relies on clusters of small and efficient RISC-V cores called Snitch developed as part of the PULP platform effort. The system can be enhanced by an additional accelerator (Stencil Processing Unit) developed by Fraunhofer that integrates seamlessly into the RISC-V insfrastructure.

Matheus Cavalcante received his MSc degree in integrated electronic systems from the Grenoble Institute of Technology (Phelma) in 2018. He is currently pursuing a PhD degree in the Digital Circuits and Systems group of Prof. Benini. His research interests include vector processing and high-performance computer architectures.

VRP/VXP: VaRiable eXtended Precision RISC-V Accelerator for High-Precision

By César Fuguet-Tortolero (CEA).

Algebraic linear solvers and eigensolvers are ubiquitous in several scientific domains such as structure calculations, fluidics or finite elements. For this reason, they are proposed in mature standard and commercial libraries. Projective methods are the most popular methods for implementing both linear solvers and eigensolvers because of their scalable memory cost O(N). However, these methods are highly sensitive to numerical stability. The use of high precision (more than 128 bits) floating-point computation increases this stability and reduces the number of iterations. Current proposals for implementing high-precision computation consist in software emulation, which exhibits poor performance.

The CEA-List proposal is a hardware accelerator for high-precision computing. We developed the hardware VaRiable eXtended Precision (VRP/VXP) RISC-V accelerator that operates on floating-point numbers with up to 512 bits of significand and 18 bits of exponent. Both software and hardware topics will be discussed during the presentation.

Work on this accelerator has been founded first by the French Research National Agency (ANR) in the framework of the IMPRENUM project, and then by the European Processor Initiative (EPI) project. A first silicon prototype was implemented using the GF22FDX technology during the first phase of the EPI project, and new optimized silicon/FPGA prototypes are being developed during the second phase of this project.

PhD. César Fuguet-Tortolero joined CEA, Grenoble, France, in 2015. He is a researcher in the Laboratory of Systems-on-Chip and Advanced Technologies (LSTA) of the CEA List institute. He contributes to the High Performance Computing (HPC) team and currently leads the team in charge of the Variable Precision accelerator for the European Processor Initiative (EPI) project. His research topics include multi/many-core architectures, memory hierarchy, cache coherency and integration of heterogeneous accelerators for the HPC domain.

How much score could a CoreScore score if a CoreScore could score cores?

By Olof Kindgren (Qamcom Technology AB) and Klas Nordmark (2550 Engineering). (slides).

The award-winning SERV is the world's smallest RISC-V CPU. It's the perfect companion whenever you need a bit of computation and silicon real estate is at a premium. But to cite one of the great 20th century thinkers: “A CPU is only as good as its software and ecosystem”. This presentation offers an introduction to SERV, what makes it so small and where it is and can be used. We investigate how and why we put thousands of cores into a single chip using the award-giving CoreScore framework and what's in store for the future.

The award-winning Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the award-winning FuseSoc IP core package manager; the award-winning SERV RISC-V CPU and SweRVolf, a reference platform for the SweRV CPU family. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike. In recent years he is also involved in the RVFPGA computer architecture course and serve as a RISC-V ambassador

Klas Nordmark is a digital design and embedded software engineer at 2550 Engineering, a part of the Qamcom group, with experience within telecom, automotive and computer vision. After having exclusively done proprietary industry work, an interest in the growing area of open source FPGA tooling and the RISC-V ISA brought him into contact with Olof, doing work on taping out ASIC adaptions of the award-winning SERV CPU as well as doing some contributions to the FuseSoc project. May occasionally be heard on the ether under the callsign SA6SEK.

Atrevido: SemiDynamics Out-of-Order RISC-V Core

By Roger Espasa (Semidynamics).

In this talk we will describe Atrevido, Semidynamic's out-of-order RISC-V Application core supporting the RISC-V vector extension. We'll cover the pipeline basics, the interplay between the vector specification and out-of-order execution and we'll discuss the Gazzillion(tm) misses feature, specifically tailored to support HPC vector programs.

Roger Espasa is the founder and CEO of SemiDynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion(tm) misses, both targeted at HPC and Machine Learning. In addition, SemiDynamics architected and designed the Esperanto Technologies' 1024+ core machine-learning 7nm SoC. Prior to Semidynamics, Roger was at Broadcom working on an ARMV8 wide out-of-order core. (2014-2016). Previously, Roger worked at Intel (2002-20014) developing a vector extension for the x86 ISA, initially deployed in XeonPhi (Larrabee) which then became AVX-512. Roger also led the texture sampling unit for Larrabee. Roger then worked on Knight's Landing (14nm) and led the core for Knights Hill (10nm). Between 1999 and 2001 Roger worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture known as Tarantula. Roger got his PhD from UPC in 1997, has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions and holds 9 patents with 41 international filings.

NaxRiscv : An open-source OoO superscalar softcore

By Charles Papon (Independent). (slides).

This talk will introduce NaxRiscv, a recently developed out-of-order (OoO) RV32/64 IMACSU softcore, by presenting its architecture, performances and also its implementation (which isn't conventional).

This project has multiple goals : (1) Providing better single threaded performances compared to other cores deployed on FPGA. (2) Keeping its logic resources usage reasonable for practical deployments. (3) Hiding memory latencies to avoid the need of L2 caches. (4) Being fully featured, as it can currently run linux on hardware, JTAG support is in developpement, a FPU is planned. (5) Exploring hardware description paradigmes in which such projects can be implemented.

Charles Papon is the initiator and main contributor of a few free and open-source projects: SpinalHDL, A Scala hardware description API (2015). VexRiscv, a RISC-V in-order softcore (linux capable, 2017). SaxonSoc, a framework to build SoC (2020). NaxRiscv : A RISC-V out-of-order superscalar softcore (linux capable, 2021). Since 2020 he has worked full time as an independent, providing community and commercial support for those projects. His background is mixed between hardware and software and got his master degree in industrial systems in 2015.

Customizing RISC-V designs to unlock innovation with Codasip

By Zdeněk Přikryl (Codasip). (slides).

For many years, the semiconductor industry has benefited from shrinking process nodes to improve performance while reducing cost and power. But our industry can no longer rely on smaller silicon geometries to achieve computational improvements. Instead, we are in a world where performance, power, and price advantages must come from the architecture. With many and varied possible specialized processor architectures, processor design automation is essential to ensure that design cycles are short and cost effective. This talk discusses how Codasip enables techniques such as domain specific acceleration, heterogenous compute and HW-SW co-design. We will go through case studies that show how RISC-V designs were customized for computational workloads in different domains with Codasip Studio.

Dr. Přikryl is Chief Technology Officer at Codasip, the leader in customizable RISC-V processor IP. He played a major role in the research at Brno University of Technology which enabled the creation of the processor development tools at Codasip. Having developed the methodology, which is based on automatic generation of hardware and software development kits from processor description language, Dr. Přikryl has continued working as the chief architect of Codasip Studio for more than ten years. He has also been the architect of diverse Codasip RISC-V processor cores including but not limited to 16/32-bit architectures for IoT, 32/64-bit DSP-oriented architectures, or Linux capable architectures. All of these architectures were developed using Codasip Studio and many of them were based on the RISC-V ISA.

OpenHW CORE-V Roadmap

By Davide Schiavone (OpenHW Group). (slides).

RISC-V system-on-chips are devices built around one or more CPUs that implementes the RISC-V ISA. Thanks to RISC-V, the development of many open-source IPs, targetting different PPA figures and targets are now available for free. However, relying on open-source IPs may sound risky when targeting production-volume chips. OpenHW Group is building open-source, permissive, fully featured RISC-V IPs (called CORE-V) that cover the market needs extensively, from low-end, low-cost microcontrollers to application-class, Linux capable IPs. In this talk, we address the OpenHW Group CORE-V roadmap, which IPs we have built with industrial-quality verification and what is coming soon. We show which IP suits best your application and what useful related IPs and specification are available.

Pasquale Davide Schiavone (Davide) is a PostDoc at the Swiss Federal Institute of Technology Lausanne (EPFL) and Director of Engineering of the OpenHW Group. He obtained the Ph.D. title at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group in 2020 and the BSc. and MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016, respectively. His main activities are the RISC-V CPU design and low-power energy-efficient computer architectures for smart systems and human-machine interfaces. He visited the Centre of Bio-Inspired Technology at Imperial College London in the Next Generation Neural Interfaces group from January to June 2018. Since the Ph.D., he delivers training workshops to companies and universities. A list of his publications is available at https://scholar.google.ch/citations?user=mfZQ9zUAAAAJ&hl=en.

An Open-Source Application Core: CVA6 from the OpenHW Group

By Jérôme Quévremont (Thales).

Thales leads the CVA6 project at the OpenHW Group, to transform ETH Zürich and University of Bologna’s ARIANE famous RISC-V application core into an industrial-grade core available as open-source for the community. From the original 64-bit ARIANE design, renamed CV64A6 by OpenHW, Thales has designed a 32-bit flavor, named CV32A6, a resource-optimized version for embedded applications that need to support rich OSes like Linux. The CV32A6 exists in two versions: one optimized for ASIC design and one as a vendor-independent FPGA soft core. Both cores share the same configurable source code, written in SystemVerilog. Among other tasks, the CVA6 project includes industrial-grade verification, performance and resource optimizations, the addition of an extension interface and the support of recent Linux versions. This talk will introduce the CVA6 features, the project goals and the recent achievements.

Jérôme Quévremont graduated in telecommunications and electronics in 1995 (Télécom Bretagne, now IMT Atlantique). After developing telecom and security integrated circuits at Texas Instruments and Thales Communications, in 2007 he headed a development lab, specialized in specifying, developing and validating secure- and crypto-chips in ASIC and FPGA technologies. His main expertise is related to ASICs and systems-on-chip in the field of networks, radio, cryptography, hardware-reconfigurable platforms, multi-cores and trusted computing. In March 2020, he joined Thales Research & Technology as an architect and a project leader in the field of RISC-V and open hardware, with special interest on embedded efficient computing, functional safety and security. Jérôme has been the chair of the Functional Safety special interest group at RISC-V International since 2020. At the OpenHW Group open-source organization, he holds the position of Technical WG, vice-chair Cores TG, technical project leader for CVA6 (a RISC-V application core).

Intro to CHERI capability-based memory protection

By Simon W. Moore (Univ. of Cambridge). (slides).

Capability Hardware Enhanced RISC Instructions (CHERI) is a security extension of conventional Instruction Set Architectures that adds capabilities – unforgeable and bounded tokens. A capability is a fat pointer containing the address and metadata, including permissions and bounds. CHERI enforces spatial safety, enables temporal safety, and supports fine-grained software compartmentalization. This talk will introduce foundational CHERI concepts along with their motivations and constraints. We will review key historical design points which have led to current CHERI incarnations, and finish with a look into the future of commercial CHERI adoption.

Simon Moore is a Professor of Computer Engineering at the University of Cambridge Department of Computer Science and Technology (previously the Computer Laboratory) in England, where he conducts research and teaching in the general area of computer architecture with particular interests in secure and rigorously-engineered processors and subsystems. Professor Moore is the senior member of the Computer Architecture research group.

The CHERI-RISC-V experimental extension

By Jonathan Woodruff (Univ. of Cambridge). (slides).

[CHERI RISC-V extension.]

CHERI brings unforgeable fat pointers, aka capabilities, into the instruction set. CHERI was originally developed as an extension to the MIPS instruction set, and we have now developed a second-generation CHERI extension for the RISC-V instruction set. CHERI-RISC-V moves to a unified register file, where integer registers are extended to hold capabilities. This naturally enables existing loads and stores to use capability addresses, saving encoding space and improving comparability between capability and traditional executables. CHERI-RISC-V also naturally extends all address CSRs to capabilities and adds a few additional capabilities to constrain capability-oblivious executables. We review design choices with their justifications, setting the stage for eventual discussions toward a ratified extension.

Jonathan Woodruff is a Senior Research Associate with expertise in processor architecture and microarchitecture as well as low-level software optimisation. Specialising in capability processor design, he has pushed into full-system optimisations including cache hierarchy, core timing, and multi-core designs as well as explorations into major security approaches including control flow integrity and private execution.

Four CHERI RISC-V micro-architectures

By Peter Rugg (Univ. of Cambridge). (slides).

After the successful initial implementation of CHERI on a MIPS processor, RISC-V offered the ideal platform to bring CHERI more actively to the research community. We augment four microarchitectures with the security extension: Bluespec Inc’s Piccolo, Flute, and Toooba (based on MIT’s RiscyOO), and lowRISC’s Ibex core. These implementations span the processor space from small area-sensitive microcontrollers to large out-of-order superscalar designs. This has allowed concrete investigation of the ISA design-space, software experimentation and given early ideas of FPGA power, performance and area overheads of supporting capabilities in different points on the processor design-space.

Peter Rugg Peter Rugg is a PhD student at University of Cambridge's Department of Computer Science and Technology supervised by Prof Simon Moore. His focus has been on extending RISC-V cores with CHERI security extensions. He has also been investigating architectural acceleration of temporal safety.

Software Ecosystem: QEMU, LLVM, CheriBSD

By Alexander Richardson (Google, Univ. of Cambridge). (slides).

The long-running CHERI project has produced an extensive collection of software and support tools. CHERI-LLVM can compile the vast majority of C and C++ programs to pure-capability executables to run on CHERI-RISC-V, as well as other CHERI architectures. CHERI-LLVM warnings and errors have been matured over many development cycles to ease the transition to dynamic memory safety enforcement, and several angles of more aggressive enforcement are available through compiler flags. Development is often eased using QEMU with CHERI-RISC-V support for quickly testing changes. CheriBSD on CHERI-RISC-V is routinely run with all user-space executables in pure-capability mode, and the kernel itself can also be compiled as a pure-capability executable. CheriBSD also implements Cornucopia temporal memory safety service for pure-capability executables. While CHERI-RISC-V has been a research platform, its software ecosystem is relatively mature and useful for general development.

Alexander Richardson is a recent graduate and post-doctoral researcher from the University of Cambridge with a doctorate dissertation extending LLVM to provide complete spatial safety for C and C++ using CHERI capabilities. Alex has also ported many C and C++ programs to CHERI while streamlining compiler feedback. Alexander Richardson is currently a Software Engineer at Google.

Demo: Detecting and Resolving an Exploit under CheriBSD on a Multi-core, Superscalar Softcore

By Franz Fuchs (Univ. of Cambridge). (slides).

We will tour the differences that CHERI introduces the familiar workflow of compiling and debugging programs. We will begin with displaying the properties of pointers on riscv64 versus a pure-capability application binary interface (ABI), and proceed to a demonstration of distinguishing pointers from data at runtime, despite identical values. We will then demonstrate the dynamic detection of a stack buffer overflow with the GDB tooling to characterise the failure. Finally we will demonstrate the extensive compiler warning support to aid in porting applications to the pure-capability ABI.

Franz Fuchs is a PhD student at the University of Cambridge Department of Computer Science and Technology supervised by Prof. Simon Moore. He has a broad interest in security with his research focus on transient-execution attacks. Franz has engaged in research to conduct attacks on a superscalar out-of-order CHERI processor and concentrates currently on defence mechanisms for capability machines.

Introduction and program of the “RISC-V International Day”

By Calista Redmond (RISC-V International).

The “Spring 2022 RISC-V Week” is made of two events, the “4th RISC-V Meeting”, which is about to close, and the “RISC-V International Day” on tomorrow, May 5. This presentation will provide an overview of the program and the speeches of the latter event.

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

Closing remarks for the “4th RISC-V Meeting”, and timing and directions to the diner cruise

By Christian Fabre (CEA, IRT-Nanoelec). (slides).

Closing remarks, statistics and acknowledgements for the “4th RISC-V Meeting” followed by schedule and directions to the dinner cruise.

Christian Fabre is Senior Research Engineer in the digital architecture and IC design department in the research technology division of CEA. He is currently part of the team working on EPI's VaRiable eXtended Precision (VRP/VXP) RISC-V accelerator that operates on floating-point numbers with up to 512 bits of significand and 18 bits of exponent. His background is in compilation, operating system, and object-oriented UML modeling. He is the General Chair of the “RISC-V Week” series of conferences.

Organizers and Sponsors

Sponsors of the “Spring 2022 RISC-V Week”

The Platinum sponsors of the Spring 2022 RISC-V Week are:

OpenHW Group logo
SiFive logo

The Gold sponsors of the Spring 2022 RISC-V Week are:

Thales logo
HUAWEI logo

The Silver sponsors of the Spring 2022 RISC-V Week are:

E4 Computer Engineering logo
SiPearl logo

Organizers of the “4th RISC-V Meeting”

 

The organizers of the 4th RISC-V Meeting are

 
CEA logo
 
IRT NanoElec logo