Poster Sessions
You will find below:
- The list of accepted posters.
- Important instructions to authors of selected posters.
- The orginal, and now closed, call for posters.
Posters will be presented in two sessions:
- The first session will start on Tuesday May 3 at 09h00, and will lasts until Wednesday 4 at 10h30 – the end of the morning break.
- The second session will start sometime after the same morning break on Wednesday 4 at 10h30, and will last until the afternoon break on the next day, that is Thursday May 5, at 15h30.
A brief overview of the poster sessions will be given by Kevin Martin in plenary, Tuesday May 3 at 09h25.
First Poster Session
The first poster session will start on Tuesday May 3 at 09h00, and will last until Wednesday 4 at 10h30 – the end of the morning break.
Enabling RISC-V in Large Scale FPGA Platforms
By Daniel J. Mazure, Alexander Kropotov, Francelly Cano, Bachir Fradj, Elias Perdomo, Alexander Fell, Teresa Cervero, John Davis (Barcelona Supercomputing Center).
RVfpga: Understanding - Computer Architecture
By Daniel Chaver (University Complutense of Madrid) and Sarah Harris (University of Nevada Las Vegas) and Zubair Kakakhel (AZKY Tech Labs) and Hamza Liaqat (AZKY Tech Labs) and Robert Owen (Imagination Technologies) and Olof Kindgren (Qamcom Research & Technology) and Luis Pinuel (University Complutense of Madrid) and Ivan Kravets (Platform IO) and Valerii Koval (Platform IO) and Ted Marena (Western Digital) and Roy Kravitz (Portland State University)
Direct Convolution: Performance Effects of Loops Ordering and Parallelization
By Mirco Mannino (Department of Information Engineering and Mathematics, University of Siena, Italy) and Andrea Mondelli (Huawei Technologies Research Development (UK) Ltd, Cambridge, England, United Kingdom) and Sandro Bartolini (Department of Information Engineering and Mathematics, University of Siena, Italy)
A RISC-V Heterogeneous SoC for Embedded Devices
By Luca Valente (DEI, University of Bologna, Italy) and Mattia Sinigaglia (DEI, University of Bologna, Italy) and Yvan Tortorella (DEI, University of Bologna, Italy) and Davide Rossi (DEI, University of Bologna, Italy) and Luca Benini (DEI, University of Bologna, Italy and IIS lab, ETH Zurich, Switzerland)
Comet: a RISC-V Core Synthesized from C++ Specifications
By Simon Rokicki (Univ Rennes, Inria, IRISA) and Joseph Paturel (Univ Rennes, Inria, IRISA) and Olivier Sentieys (Univ Rennes, Inria, IRISA)
SCI-FI: Control Signal, Code, and Control Flow Integrity against Fault Injection Attacks
By Thomas Chamelot (CEA, List) and Damien Couroussé (CEA, List) and Karine Heydemann (Sorbonne Univesité, LIP6)
An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level
By Masoud Nouripayam (Dept. of Electrical and Information Technology, Lund University, Sweden) and Arturo Prieto (Dept. of Electrical and Information Technology, Lund University, Sweden) and Vignajeth Kuttuva Kishorelal (Dept. of Electrical and Information Technology, Lund University, Sweden) and Joachim Rodrigues (Dept. of Electrical and Information Technology, Lund University, Sweden)
(abstract).
MINOTAuR: A Timing-Predictable Open Source RISC-V Core Featuring Speculative Execution
By Alban Gruin (IRIT — Université Toulouse 3 — CNRS) and Thomas Carle (IRIT — Université Toulouse 3 — CNRS) and Christine Rochange (IRIT — Université Toulouse 3 — CNRS) and Pascal Sainrat (IRIT — Université Toulouse 3 — CNRS)
Implementing Functional Safety in a RISC-V Interleaved-Multi-Threading Processor Core
By Marcello Barbirotta (Sapienza University of Rome, Italy) and Abdallah Cheikh (Sapienza University of Rome, Italy) and Antonio Mastrandrea (Sapienza University of Rome, Italy) and Francesco Menichelli (Sapienza University of Rome, Italy) and Mauro Olivieri (Sapienza University of Rome, Italy)
Formal Analysis of Fault Injection Effects on RISC-V Microarchitecture Models
By Simon Tollec (Univ. Paris-Saclay, CEA, List) and Mihail Asavoae (Univ. Paris-Saclay, CEA, List) and Damien Couroussé (Univ. Grenoble Alpes, CEA, List) and Mathieu Jan (Univ. Paris-Saclay, CEA, List) and Karine Heydemann (Sorbonne Univ., CNRS, LIP6)
Open Hardware for Near-Sensor Signal Processing and Machine Learning
By Faye Joseph (IETR - UMR CNRS 6164, INSA Rennes, FRANCE) and Maxime Pelcat (IETR - UMR CNRS 6164, INSA Rennes, FRANCE) and Jean-François Nezan (IETR - UMR CNRS 6164, INSA Rennes, FRANCE) and Kevin Martin (Univ. Bretagne-Sud, UMR CNRS 6285, Lab-STICC F-56100 Lorient, France) and Shuvra S. Bhattacharyya (University of Maryland, College Park, USA)
A RISC-V VPU for Very Long and Sparse Vectors
By Gopinath Mahale (Barcelona Supercomputing Center) and Karim Charfi (Barcelona Supercomputing Center) and Tejas Limbasiya (Barcelona Supercomputing Center) and Teresa Cervero (Barcelona Supercomputing Center) and John Davis (Barcelona Supercomputing Center)
Energy-Efficient Application-Specific Instruction-Set Processor for Feature Extraction in Smart Vision Systems
By Lucas Ferreira (Electrical and Information Technology Department, Lund University, Sweden) and Steffen Malkowsky (Electrical and Information Technology Department, Lund University, Sweden) and Patrik Persson (Mathematics Department, Lund University, Sweden) and Sven Karlsson (DTU Compute, Technical University of Denmark, Denmark) and Karl Åström (Mathematics Department, Lund University, Sweden) and Liang Liu (Electrical and Information Technology Department, Lund University, Sweden)
Variability-aware Deep Sub-micron Low- energy Designs for IoT RISC-V Processors
By Bob Vanhoof (MICAS – ESAT – KU Leuven) and Clara Nieto Taladriz Moreno (MICAS – ESAT – KU Leuven) and Wim Dehaene (MICAS – ESAT – KU Leuven)
RISC-V Virtualization for a CVA6-based SoC
By Bruno Sá (Centro Algoritmi - University of Minho DEI) and Luca Valente (DEI, University of Bologna, Italy) and José Martins (Centro Algoritmi - University of Minho DEI) and Davide Rossi (DEI, University of Bologna, Italy) and Luca Benini (DEI, University of Bologna, Italy and IIS lab, ETH Zurich, Switzerland) and Sandro Pinto (Centro Algoritmi - University of Minho DEI)
Pipeline Datapath Models from RISC-V based cores
By Samira Ait Bensaid (Université Paris-Saclay, CEA, List, F-91120, Palaiseau, France) and Mihail Asavoae (Université Paris-Saclay, CEA, List, F-91120, Palaiseau, France) and Farhat Thabet (Université Paris-Saclay, CEA, List, F-91120, Palaiseau, France) and Mathieu Jan (Université Paris-Saclay, CEA, List, F-91120, Palaiseau, France).
An Application Specific Processor for CNN-Based Massive MIMO Positioning
By Mohammad Attari (Dept. of Electrical and Information Technology, Lund University, Sweden) and Jesús Rodriguez Sánchez (Dept. of Electrical and Information Technology, Lund University, Sweden) and Liang Liu (Dept. of Electrical and Information Technology, Lund University, Sweden) and Steffen Malkowsky (Dept. of Electrical and Information Technology, Lund University, Sweden)
Accelerating applications with RISC-V Systolic Array Coprocessors
By Igor Piljić (University of Zagreb, Croatia) and Luka Mrković (University of Zagreb, Croatia) and Mate Kovač (University of Zagreb, Croatia) and Mario Kovač (University of Zagreb, Croatia) and Mehmet Alp Sarkisla (TÜBİTAK BİLGEM Kocaeli, Turkey) and Can Kurt (TÜBİTAK BİLGEM Kocaeli, Turkey) and Hikmet Öztürk (TÜBİTAK BİLGEM Kocaeli, Turkey) and Said Seferbey (TÜBİTAK BİLGEM Kocaeli, Turkey) and Alexander Fell (Barcelona Supercomputing Center) and Roger Ferrer (Barcelona Supercomputing Center) and Teresa Cervero (Barcelona Supercomputing Center) and John Davies (Barcelona Supercomputing Center)
A memory hierarchy protected against Side-channel Attacks
By Ezinam Talaki (Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France) and Olivier Savry (Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France) and David Hely (Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France) and Mathieu Bouvier Des Noes (Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France)
Second Poster Session
The second poster session will start sometime after the morning break on Wednesday 4 at 10h30, and will last until the afternoon break on the next day, that is Thursday May 5, at 15h30.
Noise-Free Security Assessment of Eviction Set Construction Algorithms with Randomized Caches
By Amine Jaamoum (CEA, LETI MINATEC Campus, University Grenoble Alpes) and Thomas Hiscock (CEA, LETI MINATEC Campus, University Grenoble Alpes) and Giorgio Di Natale (CNRS, Grenoble INP, TIMA, University Grenoble Alpes, Grenoble)
(abstract).
Composable Custom Extensions and Custom Function Units for RISC-V
By Jan Gray (Gray Research) and Tim Vogt (Lattice Semiconductor) and Tim Callahan (Google) and Charles Papon (SpinalHDL) and Guy Lemieux (University of British Columbia) and Maciej Kurc (Antmicro) and Karol Gugala (Antmicro)
Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary Translation
By Marie Badaroux (Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA Grenoble, France) and Frédéric Pétrot (Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA Grenoble, France)
Using the TUM Uncore Environment for RISC-V for Teaching, AI and Quantum Computing
By Martin Schulz, Alexis Engelke, and Carsten Trinitis (Technical University Münich).
Meet Monte Cimone: Exploring RISC-V High Performance Compute Clusters
By Andrea Bartolini (University of Bologna, Italy) and Federico Ficarelli (University of Bologna, CINECA, Italy) and Emanuele Parisi (University of Bologna, Italy) and Francesco Beneventi (University of Bologna, Italy) and Francesco Barchi (University of Bologna, Italy) and Daniele Gregori (E4 Company S.p.A., Italy) and Fabrizio Magugliani (E4 Company S.p.A., Italy) and Marco Cicala (E4 Company S.p.A., Italy) and Cosimo Gianfreda (E4 Company S.p.A., Italy) and Daniele Cesarini (E4 Company S.p.A., Italy) and Andrea Acquaviva (University of Bologna, Italy) and Luca Benini (University of Bologna, Italy)
An open CAD flow to optimised key gate insertion in logic locking
By Roselyne Chotin (Sorbonne Université, CNRS, LIP6) and Lilia Zaourar (Université Paris-Saclay, CEA).
Agile Design Methodology for Accelerator-Rich Cluster-based RISC-V SoC
By Gianluca Bellocchi (University of Modena and Reggio Emilia, 41125 Modena, Italy) and Alessandro Capotondi (University of Modena and Reggio Emilia, 41125 Modena, Italy) and Luca Benini (ETH Zürich, 8092 Zürich, Switzerland and University of Bologna, 40131 Bologna, Italy) and Andrea Marongiu (University of Modena and Reggio Emilia, 41125 Modena, Italy)
whISPer: Enhancing MemPool to Make an Open and General-Purpose Image Signal Processor
By Sergio Mazzola (Integrated Systems Laboratory (IIS), ETH Zürich, Zürich, Switzerland) and Samuel Riedel (Integrated Systems Laboratory (IIS), ETH Zürich, Zürich, Switzerland) and Matheus Cavalcante (Integrated Systems Laboratory (IIS), ETH Zürich, Zürich, Switzerland) and Luca Benini (Integrated Systems Laboratory (IIS), ETH Zürich, Zürich, Switzerland and DEI, University of Bologna, Bologna, Italy)
Towards Low-Power and Low Data-Rate Software-Defined Radio Baseband with RISC-V Processor for Flexibility and Security
By Mohamed El Bouazzati (Univ. Bretagne-Sud, UMR 6285, Lab-STICC F-56100 Lorient, France) and Philippe Tanguy (Univ. Bretagne-Sud, UMR 6285, Lab-STICC F-56100 Lorient, France) and Guy Gogniat (Univ. Bretagne-Sud, UMR 6285, Lab-STICC F-56100 Lorient, France)
Specialized Scalar and SIMD instructions for Error Correction Codes Decoding on RISC-V processor
By Tourres Mael (Laboratoire Lab-STICC (UMR 6285) Université de Bretagne Sud, France and Laboratoire IMS (UMR 5218) Bordeaux-INP, France) and Cyrille Chavet (Laboratoire Lab-STICC (UMR 6285) Université de Bretagne Sud, France) and Bertrand Le Gal (Laboratoire IMS (UMR 5218) Bordeaux-INP, France) and Jérémie Crenne (Laboratoire IMS (UMR 5218) Bordeaux-INP, France) and Philippe Coussy (Laboratoire Lab-STICC (UMR 6285) Université de Bretagne Sud, France)
(abstract).
Towards the next generation Heterogeneous Multi-core Multi-accelerator Architectures for Machine Learning
By Vikram Jain (MICAS, KU Leuven, Belgium) and Giuseppe Sarda (MICAS, KU Leuven, Imec, Belgium) and Pouya Houshmand (MICAS, KU Leuven, Belgium) and Marian Verhelst (MICAS, KU Leuven, Imec, Belgium)
(abstract).
Deterministic Cache Coherent ManyCore Environment for Embedded Systems
By Alaa Ibrahim (DEI, University of Bologna, Italy) and Gianmacro Ottavi (DEI, University of Bologna, Italy) and Luca Benini (DEI, University of Bologna, Italy and IIS lab, ETH Zurich, Switzerland) and Davide Rossi (DEI, University of Bologna, Italy)
(abstract).
RISC-V based Embedded Systems For Always-on Energy Efficient Smart Sensing with TinyML
By Lukas Schulthess (Dep. Of Information technology and Electrical Engineering ETH Zurich, Switzerland) and Tommaso Polonelli (Dep. Of Information technology and Electrical Engineering ETH Zurich, Switzerland) and Michele Magno (Dep. Of Information technology and Electrical Engineering ETH Zurich, Switzerland)
(abstract).
Automatic RISC-V Processor Synthesis using Speculative Pipelining
By Jean-Michel Gorius (Univ Rennes, Inria, CNRS, IRISA) and Simon Rokicki (Univ Rennes, Inria, CNRS, IRISA) and Steven Derrien (Univ Rennes, Inria, CNRS, IRISA)
Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor
By Gaëtan Leplus (LETI CEA Grenoble, France) and Olivier Savry (LETI CEA Grenoble, France) and Lilian Bossuet (Laboratoire Hubert Curien Jean Monnet University Saint-Etienne, France)
(abstract).
Removing Load-use dependencies bottleneck from CVA6 application class core
By Gianmarco Ottavi (DEI, University of Bologna, Italy) and Davide Rossi (DEI, University of Bologna, Italy) and Luca Benini (DEI, University of Bologna, Italy and IIS lab, ETH Zurich, Switzerland)
(abstract).
Experimental evaluation of neutron-induced errors on a RISCV processor
By Fernando Fernandes dos Santos (French Institute for Research in Computer Science and Automation (INRIA)) and Angeliki Kritikakou (French Institute for Research in Computer Science and Automation (INRIA)) and Olivier Sentieys (French Institute for Research in Computer Science and Automation (INRIA))
Graph Analytics on RISC-V GPU: Where are the Bottlenecks?
By Nimish Shah (ESAT-MICAS, KU Leuven) and Marian Verhelst (ESAT-MICAS, KU Leuven)
ControlPULP: A Multi-Core RISC-V Power Controller for HPC Processors
By Alessandro Ottaviano (ETH Zürich, Zürich, Switzerland) and Robert Balas (ETH Zürich, Zürich, Switzerland) and Giovanni Bambini (DEI, University of Bologna, Italy) and Davide Rossi (DEI, University of Bologna, Italy) and Luca Benini (DEI, University of Bologna, Italy and IIS lab, ETH Zurich, Switzerland) and Andrea Bartolini (DEI, University of Bologna, Italy)
Information for authors of selected posters
One of the authors, at least, shall register for on-site attendance to the full RISC-V Week and participate to the poster sessions. Posters will be displayed over the three days, and shall be brought by the presenting author – i.e. there is no printing service on site.
Posters shall be of A0 size, in portrait format.
The poster will be clipped on the whole length at the top – adhesive tape, pins, or other bonding system will not be allowed. A similar clamp will be used at the bottom as a counterweight.
The paper should be thick enough to support the clipping system (which it usually is) and thin enough to remain flat with just a bottom clamp (which may not be the case with laminated paper). For the clipping to work, there shall be no eyelet (œillets in French) in the corners, as they would prevent the clipping mechanism from closing properly.
The poster PDFs can also be placed online on the Spring 2022 RISC-V Week web site, at the discretion of the authors. For this, the PDF of the displayed A0 poster shall be sent to webmaster@open-src-soc.org before the end of the conference.
The call for posters (closed)
The Spring 2022 RISC-V Week will be held in Paris on May 3-5, 2022. As part of the event, a poster session will be organized and will last the three days.
This will be the opportunity for presenters to share their work on RISC-V, open source hardware, and support technologies for open source hardware such as CAD tools, operating systems, compilers, formal verification, etc. The focus will be on outcomes from Masters, PhD and Post-Doc. Results from collaborative research project and advance developments from the industry are also welcome.
As for the rest of the week, the goal is to foster discussions and enable new collaborations between industrial and academic on RISC-V and open source hardware.
We invite prospective authors to submit 1-page abstracts related to open hardware or RISC-V, in areas including, but not limited to:
- Architectures
- Security and safety
- Formal verification
- Operating systems
- Compilation
- CAD tools
Poster abstracts submissions will be processed through EasyChair. The submission format is free, but abstracts must be limited to one page, be provided as a PDF file, and shall contain as a minimum: a title, names of the authors, their affiliations, and a description of the content. Posters can be based on an already published work. If so, the original work shall be cited. One of the authors should be marked as a presenter and provide his email address for further contact.
Posters themselves do not need to be sent through EasyChair for selection, only abstracts.
Once accepted, abstracts will be put online on this site after a one-week delay for minors revisions. The poster PDFs can also be placed online at a later date, at the discretion of the authors. One of the authors, at least, shall register for on-site attendance to the full RISC-V Week and participate to the poster sessions. Printed posters will be displayed over the three days, and shall be brought by the presenting author.
In case you would like to make a demo while presenting your poster, please contact us and describe the demo and your equipment, as demo space will be limited.
Important dates and submission information:
- Poster submission:
April 1stApril 6th, 2022. - Notification of acceptance:
April 10thApril 13th, 2022, before 15:00. - Spring 2022 RISC-V Week: May 3-5, 2022, Paris.
- Submission link:
https://easychair.org/conferences/?conf=2022riscvmeetings. - Further questions:
posters@open-src-soc.org.
In case the RISC-V Week is finally held online, the poster session will be organized as a virtual event on an online platform.
The organizers of the Spring 2022 RISC-V Week are
